Import trimming

diff --git a/compiler/coreSyn/CorePrep.lhs b/compiler/coreSyn/CorePrep.lhs
index e2b6ecf..fee95a5 100644 (file)
--- a/compiler/coreSyn/CorePrep.lhs
+++ b/compiler/coreSyn/CorePrep.lhs
@@ -34,9 +34,6 @@ import ErrUtils
 import DynFlags
 import Util
 import Outputable
-import TysWiredIn
-import MkId
-import TysPrim
 \end{code}
 
 -- ---------------------------------------------------------------------------

diff --git a/compiler/coreSyn/CoreSyn.lhs b/compiler/coreSyn/CoreSyn.lhs
index d89f542..09e41aa 100644 (file)
--- a/compiler/coreSyn/CoreSyn.lhs
+++ b/compiler/coreSyn/CoreSyn.lhs
@@ -54,7 +54,6 @@ import Var
 import Type
 import Coercion
 import Name
-import OccName
 import Literal
 import DataCon
 import BasicTypes

diff --git a/compiler/specialise/Rules.lhs b/compiler/specialise/Rules.lhs
index 4b7e926..bcb847a 100644 (file)
--- a/compiler/specialise/Rules.lhs
+++ b/compiler/specialise/Rules.lhs
@@ -35,7 +35,7 @@ import IdInfo         ( SpecInfo( SpecInfo ) )
 import Var             ( Var )
 import VarEnv
 import VarSet
-import Name            ( Name, NamedThing(..), nameOccName )
+import Name            ( Name, NamedThing(..) )
 import NameEnv
 import Unify           ( ruleMatchTyX, MatchEnv(..) )
 import BasicTypes      ( Activation, CompilerPhase, isActive )