This makes about half the tests in codeGen/should_run work.
#if sparc_TARGET_ARCH
+-- getRegister :: CmmExpr -> NatM Register
+
+-- Load a literal float into a float register.
+-- The actual literal is stored in a new data area, and we load it
+-- at runtime.
getRegister (CmmLit (CmmFloat f W32)) = do
+
+ -- a label for the new data area
lbl <- getNewLabelNat
+ tmp <- getNewRegNat II32
+
let code dst = toOL [
+ -- the data area
LDATA ReadOnlyData
[CmmDataLabel lbl,
CmmStaticLit (CmmFloat f W32)],
- SETHI (HI (ImmCLbl lbl)) dst,
- LD FF32 (AddrRegImm dst (LO (ImmCLbl lbl))) dst]
+
+ -- load the literal
+ SETHI (HI (ImmCLbl lbl)) tmp,
+ LD II32 (AddrRegImm tmp (LO (ImmCLbl lbl))) dst]
+
return (Any FF32 code)
getRegister (CmmLit (CmmFloat d W64)) = do
lbl <- getNewLabelNat
+ tmp <- getNewRegNat II32
let code dst = toOL [
LDATA ReadOnlyData
[CmmDataLabel lbl,
CmmStaticLit (CmmFloat d W64)],
- SETHI (HI (ImmCLbl lbl)) dst,
- LD FF64 (AddrRegImm dst (LO (ImmCLbl lbl))) dst]
+ SETHI (HI (ImmCLbl lbl)) tmp,
+ LD II64 (AddrRegImm tmp (LO (ImmCLbl lbl))) dst]
return (Any FF64 code)
getRegister (CmmMachOp mop [x]) -- unary MachOps
r <- getRegister src
return $ case r of
Any _ code -> code dst
- Fixed _ freg fcode -> fcode `snocOL` OR False g0 (RIReg dst) freg
+ Fixed _ freg fcode -> fcode `snocOL` OR False g0 (RIReg freg) dst
where
dst = getRegisterReg reg
#if sparc_TARGET_ARCH /* || powerpc_TARGET_ARCH */
data Size
= II8 -- byte (signed)
- | II8u -- byte (unsigned)
+-- | II8u -- byte (unsigned)
| II16 -- halfword (signed, 2 bytes)
- | II16u -- halfword (unsigned, 2 bytes)
+-- | II16u -- halfword (unsigned, 2 bytes)
| II32 -- word (4 bytes)
| II64 -- word (8 bytes)
| FF32 -- IEEE single-precision floating pt
intSize, floatSize :: Width -> Size
intSize W8 = II8
-intSize W16 = II16u
+--intSize W16 = II16u
+intSize W16 = II16
intSize W32 = II32
intSize W64 = II64
intSize other = pprPanic "MachInstrs.intSize" (ppr other)
sizeToWidth size
= case size of
II8 -> W8
- II8u -> W8
+-- II8u -> W8
II16 -> W16
- II16u -> W16
+-- II16u -> W16
II32 -> W32
II64 -> W64
FF32 -> W32
#if sparc_TARGET_ARCH
freeReg g0 = fastBool False -- %g0 is always 0.
+
freeReg g5 = fastBool False -- %g5 is reserved (ABI).
freeReg g6 = fastBool False -- %g6 is reserved (ABI).
freeReg g7 = fastBool False -- %g7 is reserved (ABI).
freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
freeReg f1 = fastBool False
+
+-- TODO: Not sure about these BL 2009/01/10
+-- Used for NCG spill tmps? what is this?
+
+{-
+freeReg g1 = fastBool False -- %g1 is used for NCG spill tmp
+freeReg g2 = fastBool False
+freeReg f6 = fastBool False
+freeReg f8 = fastBool False
+freeReg f26 = fastBool False
+freeReg f27 = fastBool False
+-}
+
#endif
#if powerpc_TARGET_ARCH
-- -----------------------------------------------------------------------------
--- pprSize: print a 'Size'
+-- | print a 'Size'
+-- Used for instruction suffixes.
+-- eg LD is 32bit on sparc, but LDD is 64 bit.
+--
#if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH || sparc_TARGET_ARCH
pprSize :: Size -> Doc
II8 -> sLit "sb"
II16 -> sLit "sh"
II32 -> sLit ""
+ II64 -> sLit "d"
FF32 -> sLit ""
FF64 -> sLit "d"
)
pprInstr :: Instr -> Doc
---pprInstr (COMMENT s) = empty -- nuke 'em
+pprInstr (COMMENT s) = empty -- nuke 'em
+{-
pprInstr (COMMENT s)
= IF_ARCH_alpha( ((<>) (ptext (sLit "\t# ")) (ftext s))
- ,IF_ARCH_sparc( ((<>) (ptext (sLit "! ")) (ftext s))
+ ,IF_ARCH_sparc( ((<>) (ptext (sLit "# ")) (ftext s))
,IF_ARCH_i386( ((<>) (ptext (sLit "# ")) (ftext s))
,IF_ARCH_x86_64( ((<>) (ptext (sLit "# ")) (ftext s))
,IF_ARCH_powerpc( IF_OS_linux(
((<>) (ptext (sLit "# ")) (ftext s)),
((<>) (ptext (sLit "; ")) (ftext s)))
,)))))
-
+-}
pprInstr (DELTA d)
= pprInstr (COMMENT (mkFastString ("\tdelta = " ++ show d)))
]
pprInstr (ADD x cc reg1 ri reg2)
- | not x && not cc && riZero ri
- = hcat [ ptext (sLit "\tmov\t"), pprReg reg1, comma, pprReg reg2 ]
+-- | not x && not cc && riZero ri
+-- = hcat [ ptext (sLit "\tmov\t"), pprReg reg1, comma, pprReg reg2 ]
+
| otherwise
= pprRegRIReg (if x then sLit "addx" else sLit "add") cc reg1 ri reg2
pprInstr (ANDN b reg1 ri reg2) = pprRegRIReg (sLit "andn") b reg1 ri reg2
pprInstr (OR b reg1 ri reg2)
- | not b && reg1 == g0
+{- | not b && reg1 == g0
= let doit = hcat [ ptext (sLit "\tmov\t"), pprRI ri, comma, pprReg reg2 ]
in case ri of
RIReg rrr | rrr == reg2 -> empty
other -> doit
+-}
| otherwise
= pprRegRIReg (sLit "or") b reg1 ri reg2