NCG: Comments and formatting only

diff --git a/compiler/nativeGen/RegAlloc/Graph/ArchBase.hs b/compiler/nativeGen/RegAlloc/Graph/ArchBase.hs
index 6d31220..6172cde 100644 (file)
--- a/compiler/nativeGen/RegAlloc/Graph/ArchBase.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/ArchBase.hs
@@ -23,8 +23,6 @@ module RegAlloc.Graph.ArchBase (
 )
        
 where
-
------
 import UniqSet
 import Unique
 
@@ -32,7 +30,6 @@ import Unique
 -- Some basic register classes.
 --     These aren't nessesarally in 1-to-1 correspondance with the allocatable
 --     RegClasses in MachRegs.hs
---
 data RegClass
        -- general purpose regs
        = ClassG32      -- 32 bit GPRs
@@ -85,7 +82,6 @@ data RegSub
 
 -- This should be hand coded/cached for each particular architecture,
 --     because the compute time is very long..
-
 worst 
        :: (RegClass    -> UniqSet Reg)
        -> (Reg         -> UniqSet Reg)
@@ -114,8 +110,6 @@ worst regsOfClass regAlias neighbors classN classC
 -- | For a node N of classN and neighbors of classesC
 --     (bound classN classesC) is the maximum number of potential 
 --     colors for N that can be lost by coloring its neighbors.
---
-
 bound 
        :: (RegClass    -> UniqSet Reg)
        -> (Reg         -> UniqSet Reg)
@@ -139,8 +133,7 @@ bound regsOfClass regAlias classN classesC
 --
 --     A version of this should be constructed for each particular architecture,
 --     possibly including uses of bound, so that alised registers don't get counted
---     twice, as per the paper.
---     
+--     twice, as per the paper.        
 squeese 
        :: (RegClass    -> UniqSet Reg)
        -> (Reg         -> UniqSet Reg)

diff --git a/compiler/nativeGen/RegAlloc/Graph/ArchX86.hs b/compiler/nativeGen/RegAlloc/Graph/ArchX86.hs
index 8018f24..e12d62d 100644 (file)
--- a/compiler/nativeGen/RegAlloc/Graph/ArchX86.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/ArchX86.hs
@@ -31,7 +31,6 @@ classOfReg reg
 
        
 -- | Determine all the regs that make up a certain class.
---
 regsOfClass :: RegClass -> UniqSet Reg
 regsOfClass c
  = case c of
@@ -52,7 +51,6 @@ regsOfClass c
 
 -- | Determine the common name of a reg
 --     returns Nothing if this reg is not part of the machine.
-       
 regName :: Reg -> Maybe String
 regName reg
  = case reg of

diff --git a/compiler/nativeGen/RegAlloc/Graph/Coalesce.hs b/compiler/nativeGen/RegAlloc/Graph/Coalesce.hs
index e0fad17..556f91c 100644 (file)
--- a/compiler/nativeGen/RegAlloc/Graph/Coalesce.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/Coalesce.hs
@@ -25,7 +25,6 @@ import Data.List
 --     For Reg -> Reg moves, if the first reg dies at the same time the second reg is born
 --     then the mov only serves to join live ranges. The two regs can be renamed to be 
 --     the same and the move instruction safely erased.
-
 regCoalesce 
        :: Instruction instr
        => [LiveCmmTop instr] 
@@ -60,7 +59,6 @@ sinkReg fm r
 -- | Slurp out mov instructions that only serve to join live ranges.
 --     During a mov, if the source reg dies and the destiation reg is born
 --     then we can rename the two regs to the same thing and eliminate the move.
---
 slurpJoinMovs 
        :: Instruction instr
        => LiveCmmTop instr 

diff --git a/compiler/nativeGen/RegAlloc/Graph/Main.hs b/compiler/nativeGen/RegAlloc/Graph/Main.hs
index 069c8c0..cdbe987 100644 (file)
--- a/compiler/nativeGen/RegAlloc/Graph/Main.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/Main.hs
@@ -43,7 +43,6 @@ maxSpinCount  = 10
 
 
 -- | The top level of the graph coloring register allocator.
---     
 regAlloc
        :: (Outputable instr, Instruction instr)
        => DynFlags
@@ -169,9 +168,6 @@ regAlloc_spin
                --      and rewrite SPILL/RELOAD pseudos into real instructions along the way
                let code_final          = map stripLive code_spillclean
 
---             let spillNatTop         = mapGenBlockTop spillNatBlock
---             let code_final          = map spillNatTop code_nat
-               
                -- record what happened in this stage for debugging
                let stat                =
                        RegAllocStatsColored
@@ -240,9 +236,7 @@ regAlloc_spin
                        code_relive
 
 
-
 -- | Build a graph from the liveness and coalesce information in this code.
-
 buildGraph 
        :: Instruction instr
        => [LiveCmmTop instr]
@@ -270,7 +264,6 @@ buildGraph code
 
 -- | Add some conflict edges to the graph.
 --     Conflicts between virtual and real regs are recorded as exclusions.
---
 graphAddConflictSet 
        :: UniqSet Reg
        -> Color.Graph VirtualReg RegClass RealReg
@@ -293,7 +286,6 @@ graphAddConflictSet set graph
 
 -- | Add some coalesence edges to the graph
 --     Coalesences between virtual and real regs are recorded as preferences.
---
 graphAddCoalesce 
        :: (Reg, Reg) 
        -> Color.Graph VirtualReg RegClass RealReg

diff --git a/compiler/nativeGen/RegAlloc/Graph/Stats.hs b/compiler/nativeGen/RegAlloc/Graph/Stats.hs
index 9fed1eb..51554d6 100644 (file)
--- a/compiler/nativeGen/RegAlloc/Graph/Stats.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/Stats.hs
@@ -1,8 +1,6 @@
 {-# OPTIONS -fno-warn-missing-signatures #-}
--- Carries interesting info for debugging / profiling of the 
+-- | Carries interesting info for debugging / profiling of the 
 --     graph coloring register allocator.
---
-
 module RegAlloc.Graph.Stats (
        RegAllocStats (..),
 
@@ -89,20 +87,12 @@ instance Outputable instr => Outputable (RegAllocStats instr) where
        $$ (ppr (raCode s))
        $$ text ""
 
---     $$ text "#  Register conflict graph."
---     $$ Color.dotGraph regDotColor trivColorable (raGraph s)
---     $$ text ""
-
        $$ (if (not $ isNullUFM $ raCoalesced s)
                then    text "#  Registers coalesced."
                        $$ (vcat $ map ppr $ ufmToList $ raCoalesced s)
                        $$ text ""
                else empty)
 
---     $$ text "#  Spill costs.  reg uses defs lifetime degree cost"
---     $$ vcat (map (pprSpillCostRecord (raGraph s)) $ eltsUFM $ raSpillCosts s)
---     $$ text ""
-
        $$ text "#  Spills inserted."
        $$ ppr (raSpillStats s)
        $$ text ""
@@ -114,10 +104,6 @@ instance Outputable instr => Outputable (RegAllocStats instr) where
  ppr (s@RegAllocStatsColored { raSRMs = (spills, reloads, moves) })
        =  text "#  Colored"
 
---     $$ text "#  Register conflict graph (initial)."
---     $$ Color.dotGraph regDotColor trivColorable (raGraph s)
---     $$ text ""
-
        $$ text "#  Code with liveness information."
        $$ (ppr (raCode s))
        $$ text ""
@@ -267,7 +253,6 @@ pprStatsLifeConflict stats graph
 
 -- | Count spill/reload/reg-reg moves.
 --     Lets us see how well the register allocator has done.
---
 countSRMs 
        :: Instruction instr
        => LiveCmmTop instr -> (Int, Int, Int)
@@ -300,18 +285,3 @@ countSRM_instr li
 addSRM (s1, r1, m1) (s2, r2, m2)
        = (s1+s2, r1+r2, m1+m2)
 
-
-
-
-
-
-{-
-toX11Color (r, g, b)
- = let rs      = padL 2 '0' (showHex r "")
-       gs      = padL 2 '0' (showHex r "")
-       bs      = padL 2 '0' (showHex r "")
-
-       padL n c s
-               = replicate (n - length s) c ++ s
-  in   "#" ++ rs ++ gs ++ bs
--}