small_bitmap = case bitmap of
[] -> 0
- [b] -> fromIntegral b
+ [b] -> b
_ -> panic "mkLiveness"
small_liveness =
fromIntegral (length bits) .|. (small_bitmap `shiftL` bITMAP_BITS_SHIFT)
= let
small_bits = case bits of
[] -> 0
- [b] -> fromIntegral b
+ [b] -> b
_ -> panic "livenessToAddrMode"
in
return (smallLiveness size small_bits)
cgTickBox mod n = do
let tick_box = (cmmIndex W64
(CmmLit $ CmmLabel $ mkHpcTicksLabel $ mod)
- (fromIntegral n)
+ n
)
stmtsC [ CmmStore tick_box
(CmmMachOp (MO_Add W64)
where
tick_box = cmmIndex W64
(CmmLit $ CmmLabel $ mkHpcTicksLabel $ mod)
- (fromIntegral n)
+ n
initHpc :: Module -> HpcInfo -> FCode CmmAGraph
-- Emit top-level tables for HPC and return code to initialise
= let
small_bits = case bits of
[] -> 0
- [b] -> fromIntegral b
+ [b] -> b
_ -> panic "livenessToAddrMode"
in
return (smallLiveness size small_bits)
| Just (tickInfo, (_annot, newRhs)) <- isTickedExp' rhs = do
code <- schemeE d 0 p newRhs
arr <- getBreakArray
- let idOffSets = getVarOffSets (fromIntegral d) p tickInfo
+ let idOffSets = getVarOffSets d p tickInfo
let tickNumber = tickInfo_number tickInfo
let breakInfo = BreakInfo
{ breakInfo_module = tickInfo_module tickInfo
releaseReg :: RealReg -> FreeRegs -> FreeRegs
releaseReg (RealRegSingle r) (FreeRegs g f)
- | r > 31 = FreeRegs g (f .|. (1 `shiftL` (fromIntegral r - 32)))
- | otherwise = FreeRegs (g .|. (1 `shiftL` fromIntegral r)) f
+ | r > 31 = FreeRegs g (f .|. (1 `shiftL` (r - 32)))
+ | otherwise = FreeRegs (g .|. (1 `shiftL` r)) f
releaseReg _ _
= panic "RegAlloc.Linear.PPC.releaseReg: bad reg"
allocateReg :: RealReg -> FreeRegs -> FreeRegs
allocateReg (RealRegSingle r) (FreeRegs g f)
- | r > 31 = FreeRegs g (f .&. complement (1 `shiftL` (fromIntegral r - 32)))
- | otherwise = FreeRegs (g .&. complement (1 `shiftL` fromIntegral r)) f
+ | r > 31 = FreeRegs g (f .&. complement (1 `shiftL` (r - 32)))
+ | otherwise = FreeRegs (g .&. complement (1 `shiftL` r)) f
allocateReg _ _
= panic "RegAlloc.Linear.PPC.allocateReg: bad reg"
allocateReg :: RealReg -> FreeRegs -> FreeRegs
allocateReg (RealRegSingle r) f
- = f .&. complement (1 `shiftL` fromIntegral r)
+ = f .&. complement (1 `shiftL` r)
allocateReg _ _
= panic "RegAlloc.Linear.X86.FreeRegs.allocateReg: no reg"