From: ross <unknown>
Date: Tue, 3 Jun 2003 09:37:15 +0000 (+0000)
Subject: [project @ 2003-06-03 09:37:14 by ross]
X-Git-Tag: Approx_11550_changesets_converted~820
X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=commitdiff_plain;h=56af76cc6a264621bfd18071f21e6a608e691e47

[project @ 2003-06-03 09:37:14 by ross]
fix for gcc 3.3 preprocessor: no layout, end-of-line comments or complex
Haskell comments in macro arguments.

please merge to STABLE
---

diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs
index e9cf788..0508888 100644
--- a/ghc/compiler/nativeGen/MachMisc.lhs
+++ b/ghc/compiler/nativeGen/MachMisc.lhs
@@ -76,11 +76,11 @@ underscorePrefix = (cLeadingUnderscore == "YES")
 fmtAsmLbl :: String -> String  -- for formatting labels
 
 fmtAsmLbl s
-  =  IF_ARCH_alpha(
      {- The alpha assembler likes temporary labels to look like $L123
 	instead of L123.  (Don't toss the L, because then Lf28
 	turns into $f28.)
      -}
+  =  IF_ARCH_alpha(
      '$' : s
      ,{-otherwise-}
      '.':'L':s
diff --git a/ghc/compiler/nativeGen/RegAllocInfo.lhs b/ghc/compiler/nativeGen/RegAllocInfo.lhs
index 56f4356..e0377b8 100644
--- a/ghc/compiler/nativeGen/RegAllocInfo.lhs
+++ b/ghc/compiler/nativeGen/RegAllocInfo.lhs
@@ -917,23 +917,23 @@ spillReg vreg_to_slot_map delta dyn vreg
 
 	{-I386: spill above stack pointer leaving 3 words/spill-}
 	,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
-                        in case regClass vreg of
-                              RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w))
-                              _         -> GST F80 dyn (spRel off_w) -- RcFloat/RcDouble
+                        in case regClass vreg of {
+                              RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w));
+                              _         -> GST F80 dyn (spRel off_w)} {- RcFloat/RcDouble -}
 
 	{-SPARC: spill below frame pointer leaving 2 words/spill-}
 	,IF_ARCH_sparc( 
-                        let off_w = 1 + (off `div` 4)
-                            sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+                        let{off_w = 1 + (off `div` 4);
+                            sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
                         in ST sz dyn (fpRel (- off_w))
         ,IF_ARCH_powerpc(
-			let sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+			let{sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
 			in ST sz dyn (AddrRegImm sp (ImmInt (off-delta)))
 	,))))
 
@@ -946,22 +946,22 @@ loadReg vreg_to_slot_map delta vreg dyn
 	 IF_ARCH_alpha( LD  sz dyn (spRel (- (off `div` 8)))
 
 	,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
-                        in case regClass vreg of
-                              RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn)
-                              _         -> GLD F80 (spRel off_w) dyn -- RcFloat/RcDouble
+                        in case regClass vreg of {
+                              RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn);
+                              _         -> GLD F80 (spRel off_w) dyn} {- RcFloat/RcDouble -}
 
 	,IF_ARCH_sparc( 
-                        let off_w = 1 + (off `div` 4)
-                            sz = case regClass vreg of
-                                   RcInteger -> W
-                                   RcFloat   -> F
-                                   RcDouble  -> DF
+                        let{off_w = 1 + (off `div` 4);
+                            sz = case regClass vreg of {
+                                   RcInteger -> W;
+                                   RcFloat   -> F;
+                                   RcDouble  -> DF}}
                         in LD sz (fpRel (- off_w)) dyn
         ,IF_ARCH_powerpc(
-			let sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+			let{sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
 			in LD sz dyn (AddrRegImm sp (ImmInt (off-delta)))
 	,))))
 \end{code}