From: Roman Leshchinskiy <rl@cse.unsw.edu.au>
Date: Fri, 25 Aug 2006 10:17:53 +0000 (+0000)
Subject: Add atomic SMP primitives for the Sparc
X-Git-Tag: Before_FC_branch_merge~126
X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=commitdiff_plain;h=846f2649419f6d008b7f14f855e51cbc112960b3

Add atomic SMP primitives for the Sparc
---

diff --git a/includes/SMP.h b/includes/SMP.h
index 91ffc22..af4174f 100644
--- a/includes/SMP.h
+++ b/includes/SMP.h
@@ -48,6 +48,13 @@ xchg(StgPtr p, StgWord w)
         :"=r" (result)
         :"r" (w), "r" (p)
     );
+#elif sparc_HOST_ARCH
+    result = w;
+    __asm__ __volatile__ (
+        "swap %1,%0"
+	: "+r" (result), "+m" (*p)
+	: /* no input-only operands */
+      );
 #elif !defined(WITHSMP)
     result = *p;
     *p = w;
@@ -84,6 +91,14 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
         :"cc", "memory"
     );
     return result;
+#elif sparc_HOST_ARCH
+    __asm__ __volatile__ (
+	"cas [%1], %2, %0"
+	: "+r" (n)
+	: "r" (p), "r" (o)
+	: "memory"
+    );
+    return n;
 #elif !defined(WITHSMP)
     StgWord result;
     result = *p;
@@ -112,6 +127,9 @@ write_barrier(void) {
     __asm__ __volatile__ ("" : : : "memory");
 #elif powerpc_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
+#elif sparc_HOST_ARCH
+    /* Sparc in TSO mode does not require write/write barriers. */
+    __asm__ __volatile__ ("" : : : "memory");
 #elif !defined(WITHSMP)
     return;
 #else