From: Ben.Lippmeier@anu.edu.au <unknown>
Date: Fri, 23 Jan 2009 00:50:51 +0000 (+0000)
Subject: SPARC NCG: Don't need a write barrier for store synchronisation on SPARC under TSO.
X-Git-Tag: 2009-03-13~136
X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=commitdiff_plain;h=bddb8ebe61ae38c4f4eb766966cf1caee7fb1de2

SPARC NCG: Don't need a write barrier for store synchronisation on SPARC under TSO.
---

diff --git a/compiler/nativeGen/MachCodeGen.hs b/compiler/nativeGen/MachCodeGen.hs
index 1cfc7a3..002adf9 100644
--- a/compiler/nativeGen/MachCodeGen.hs
+++ b/compiler/nativeGen/MachCodeGen.hs
@@ -3616,6 +3616,16 @@ genCCall
 
 -}
 
+
+-- On SPARC under TSO (Total Store Ordering), writes earlier in the instruction stream
+-- are guaranteed to take place before writes afterwards (unlike on PowerPC). 
+-- Ref: Section 8.4 of the SPARC V9 Architecture manual.
+--
+-- In the SPARC case we don't need a barrier.
+--
+genCCall (CmmPrim (MO_WriteBarrier)) _ _
+ = do	return nilOL
+
 genCCall target dest_regs argsAndHints 
  = do	 	
 	-- strip hints from the arg regs