From 8f6ef1daa3b8d843fb2559f2ae240d290aad0387 Mon Sep 17 00:00:00 2001
From: "wolfgang.thaller@gmx.net" <unknown>
Date: Mon, 11 Dec 2006 22:25:34 +0000
Subject: [PATCH] Support MO_WriteBarrier in PowerPC NCG (lwsync instruction)

---
 compiler/nativeGen/MachCodeGen.hs |    4 ++++
 compiler/nativeGen/MachInstrs.hs  |    1 +
 compiler/nativeGen/PprMach.hs     |    2 ++
 3 files changed, 7 insertions(+)

diff --git a/compiler/nativeGen/MachCodeGen.hs b/compiler/nativeGen/MachCodeGen.hs
index 85292d8a..3d7296d 100644
--- a/compiler/nativeGen/MachCodeGen.hs
+++ b/compiler/nativeGen/MachCodeGen.hs
@@ -3552,6 +3552,10 @@ outOfLineFloatOp mop =
     frame just before ccalling.
 -}
 
+
+genCCall (CmmPrim MO_WriteBarrier) _ _ _
+ = return $ unitOL LWSYNC
+
 genCCall target dest_regs argsAndHints vols
   = ASSERT (not $ any (`elem` [I8,I16]) argReps)
         -- we rely on argument promotion in the codeGen
diff --git a/compiler/nativeGen/MachInstrs.hs b/compiler/nativeGen/MachInstrs.hs
index baac1cd..9c0e71c 100644
--- a/compiler/nativeGen/MachInstrs.hs
+++ b/compiler/nativeGen/MachInstrs.hs
@@ -719,4 +719,5 @@ fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
 	      | FETCHPC Reg            -- pseudo-instruction:
 	                               -- bcl to next insn, mflr reg
 	      
+	      | LWSYNC -- memory barrier
 #endif /* powerpc_TARGET_ARCH */
diff --git a/compiler/nativeGen/PprMach.hs b/compiler/nativeGen/PprMach.hs
index f1e0240..6965bbf 100644
--- a/compiler/nativeGen/PprMach.hs
+++ b/compiler/nativeGen/PprMach.hs
@@ -2322,6 +2322,8 @@ pprInstr (FETCHPC reg) = vcat [
         hcat [ ptext SLIT("1:\tmflr\t"), pprReg reg ]
     ]
 
+pprInstr LWSYNC = ptext SLIT("\tlwsync")
+
 pprInstr _ = panic "pprInstr (ppc)"
 
 pprLogic op reg1 reg2 ri = hcat [
-- 
1.7.10.4