From bca11b6352ea379329a645df1d706e2b28378629 Mon Sep 17 00:00:00 2001
From: "Ben.Lippmeier@anu.edu.au" <unknown>
Date: Thu, 15 Jan 2009 05:57:27 +0000
Subject: [PATCH] More fixes to the SPARC native code generator

 * Fix loading of 64bit floats
 * Put SRT and other read only static data in the .text segment
---
 compiler/nativeGen/MachCodeGen.hs |   18 +++++++++---------
 compiler/nativeGen/PprMach.hs     |   16 ++++++++++------
 2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/compiler/nativeGen/MachCodeGen.hs b/compiler/nativeGen/MachCodeGen.hs
index 90285bf..6d16da8 100644
--- a/compiler/nativeGen/MachCodeGen.hs
+++ b/compiler/nativeGen/MachCodeGen.hs
@@ -31,6 +31,7 @@ import NCGMonad
 import PositionIndependentCode
 import RegAllocInfo 	( mkBranchInstr, mkRegRegMoveInstr )
 import MachRegs
+import PprMach
 
 -- Our intermediate code:
 import BlockId
@@ -58,6 +59,7 @@ import Data.Bits
 import Data.Word
 import Data.Int
 
+
 -- -----------------------------------------------------------------------------
 -- Top-level of the instruction selector
 
@@ -2592,15 +2594,13 @@ assignMem_FltCode pk addr src = do
     return code__2
 
 -- Floating point assignment to a register/temporary
--- ToDo: Verify correctness
-assignReg_FltCode pk reg src = do
-    r <- getRegister src
-    v1 <- getNewRegNat pk
-    return $ case r of
-        Any _ code         -> code dst
-	Fixed _ freg fcode -> fcode `snocOL` FMOV pk freg v1
-    where
-      dst = getRegisterReg reg
+assignReg_FltCode pk dstCmmReg srcCmmExpr = do
+    srcRegister <- getRegister srcCmmExpr
+    let dstReg	= getRegisterReg dstCmmReg
+
+    return $ case srcRegister of
+        Any _ code         	    -> code dstReg
+	Fixed _ srcFixedReg srcCode -> srcCode `snocOL` FMOV pk srcFixedReg dstReg
 
 #endif /* sparc_TARGET_ARCH */
 
diff --git a/compiler/nativeGen/PprMach.hs b/compiler/nativeGen/PprMach.hs
index eb373fe..822dc0d 100644
--- a/compiler/nativeGen/PprMach.hs
+++ b/compiler/nativeGen/PprMach.hs
@@ -482,14 +482,14 @@ pprImm (ImmFloat _)  = ptext (sLit "naughty float immediate")
 pprImm (ImmDouble _) = ptext (sLit "naughty double immediate")
 
 pprImm (ImmConstantSum a b) = pprImm a <> char '+' <> pprImm b
-#if sparc_TARGET_ARCH
+-- #if sparc_TARGET_ARCH
 -- ToDo: This should really be fixed in the PIC support, but only
 -- print a for now.
-pprImm (ImmConstantDiff a b) = pprImm a 
-#else
+-- pprImm (ImmConstantDiff a b) = pprImm a 
+-- #else
 pprImm (ImmConstantDiff a b) = pprImm a <> char '-'
                             <> lparen <> pprImm b <> rparen
-#endif
+-- #endif
 
 #if sparc_TARGET_ARCH
 pprImm (LO i)
@@ -640,7 +640,7 @@ pprSectionHeader Data
 pprSectionHeader ReadOnlyData
     = ptext
 	 (IF_ARCH_alpha(sLit "\t.data\n\t.align 3"
-	,IF_ARCH_sparc(sLit ".data\n\t.align 8" {-<8 will break double constants -}
+	,IF_ARCH_sparc(sLit ".text\n\t.align 8" {-<8 will break double constants -}
 	,IF_ARCH_i386(IF_OS_darwin(sLit ".const\n.align 2",
                                    sLit ".section .rodata\n\t.align 4")
 	,IF_ARCH_x86_64(IF_OS_darwin(sLit ".const\n.align 3",
@@ -651,7 +651,7 @@ pprSectionHeader ReadOnlyData
 pprSectionHeader RelocatableReadOnlyData
     = ptext
 	 (IF_ARCH_alpha(sLit "\t.data\n\t.align 3"
-	,IF_ARCH_sparc(sLit ".data\n\t.align 8" {-<8 will break double constants -}
+	,IF_ARCH_sparc(sLit ".text\n\t.align 8" {-<8 will break double constants -}
 	,IF_ARCH_i386(IF_OS_darwin(sLit ".const_data\n.align 2",
                                    sLit ".section .data\n\t.align 4")
 	,IF_ARCH_x86_64(IF_OS_darwin(sLit ".const_data\n.align 3",
@@ -2034,6 +2034,9 @@ pprInstr (FDIV size reg1 reg2 reg3)
   = pprSizeRegRegReg (sLit "fdiv") size reg1 reg2 reg3
 
 pprInstr (FMOV FF32 reg1 reg2) = pprSizeRegReg (sLit "fmov") FF32 reg1 reg2
+pprInstr (FMOV FF64 reg1 reg2) = pprSizeRegReg (sLit "fmov") FF64 reg1 reg2
+
+{-
 pprInstr (FMOV FF64 reg1 reg2)
  = let	Just reg1H	= fPair reg1
  	Just reg2H	= fPair reg2
@@ -2042,6 +2045,7 @@ pprInstr (FMOV FF64 reg1 reg2)
     (if (reg1 == reg2) then empty
      else (<>) (char '\n')
     	  (pprSizeRegReg (sLit "fmov") FF32 reg1H reg2H))
+-}
 
 pprInstr (FMUL size reg1 reg2 reg3)
   = pprSizeRegRegReg (sLit "fmul") size reg1 reg2 reg3
-- 
1.7.10.4