From cdddb0692ea0b181c5d85e2e0991c2552b9957aa Mon Sep 17 00:00:00 2001
From: "Ben.Lippmeier@anu.edu.au" <unknown>
Date: Fri, 24 Aug 2007 16:03:14 +0000
Subject: [PATCH] comment wibble

---
 compiler/nativeGen/PprMach.hs      |   11 -----------
 compiler/nativeGen/RegAllocInfo.hs |   12 ++++--------
 2 files changed, 4 insertions(+), 19 deletions(-)

diff --git a/compiler/nativeGen/PprMach.hs b/compiler/nativeGen/PprMach.hs
index a2ae0e3..3cdce1d 100644
--- a/compiler/nativeGen/PprMach.hs
+++ b/compiler/nativeGen/PprMach.hs
@@ -1227,17 +1227,6 @@ pprSizeRegRegReg name size reg1 reg2 reg3
 
 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
 
-{-									-- BUGS: changed for coloring allocator
-pprInstr v@(MOV size s@(OpReg src) d@(OpReg dst)) -- hack		-- write a pass for this and patch linear allocator with it
-  | src == dst
-  =
-#if 0 /* #ifdef DEBUG */
-    (<>) (ptext SLIT("# warning: ")) (pprSizeOpOp SLIT("mov") size s d)
-#else
-    empty
-#endif
--}
-
 pprInstr (SPILL reg slot)
    = hcat [
    	ptext SLIT("\tSPILL"),
diff --git a/compiler/nativeGen/RegAllocInfo.hs b/compiler/nativeGen/RegAllocInfo.hs
index 9b60fb9..f27d879 100644
--- a/compiler/nativeGen/RegAllocInfo.hs
+++ b/compiler/nativeGen/RegAllocInfo.hs
@@ -775,14 +775,12 @@ isRegRegMove _ = Nothing
 -- Generating spill instructions
 
 mkSpillInstr
-   :: Reg		-- register to spill (should be a real)
+   :: Reg		-- register to spill
    -> Int		-- current stack delta
    -> Int		-- spill slot to use
    -> Instr
 mkSpillInstr reg delta slot
- -- = ASSERT(isRealReg reg)			-- BUGS: used for graph coloring: is this ok?
-  = let	
-        off     = spillSlotToOffset slot
+  = let	off     = spillSlotToOffset slot
     in
 #ifdef alpha_TARGET_ARCH
     {-Alpha: spill below the stack pointer (?)-}
@@ -820,14 +818,12 @@ mkSpillInstr reg delta slot
 
 
 mkLoadInstr
-   :: Reg		-- register to load (should be a real)
+   :: Reg		-- register to load
    -> Int		-- current stack delta
    -> Int		-- spill slot to use
    -> Instr
 mkLoadInstr reg delta slot
- -- = ASSERT(isRealReg reg)			-- BUGS: used for graph coloring: is this ok?
-  = let
-        off     = spillSlotToOffset slot
+  = let off     = spillSlotToOffset slot
     in
 #if alpha_TARGET_ARCH
 	 LD  sz dyn (spRel (- (off `div` 8)))
-- 
1.7.10.4