doc/ivme-slides.tex

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   5                                 % (must be loaded before `fancyvrb')
   6 \usepackage{fancyhdr}           % Headers and footers definitions
   7 \usepackage{fancyvrb}           % Fancy verbatim environments
   8 \usepackage{wrapfig}
   9 \usepackage{float}
  10 \usepackage{amsmath}
  11 \usepackage{amssymb}
  12 \usepackage{pdftricks}
  13 \begin{psinputs}
  14   \usepackage{pstcol}             % PSTricks with the standard color package
  15                                   % (before `graphicx' for the \scalebox macro)
  16   \usepackage{graphicx}           % Standard graphics package
  17   \usepackage{multido}            % General loop macro
  18   \usepackage{pifont}             % Ding symbols (mainly for lists)
  19   \usepackage{pst-fr3d}           % PSTricks 3D framed boxes
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  22   \usepackage{pst-slpe}           % Improved PSTricks gradients
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  26 \definecolor{CodeBorder}{rgb}{0.6,0.6,0.6}
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  28 \usepackage{graphicx}
  29 \usepackage{fancyvrb}
  30 \usepackage{float}
  31 \usepackage{fvrb-ex}
  32 \usepackage{bold-extra}
  33 \usepackage{ulem}
  34 \usepackage{amssymb,amsmath,epsfig,alltt}
  35 \usepackage{semcolor}           % Seminar colored slides
  36 \usepackage{semhelv}            % Seminar helvetica fonts
  37 \usepackage{semlayer}           % Seminar overlays
  38 \usepackage{slidesec}           % Seminar sections and list of slides
  39 \usepackage{url}                % Convenient URL typesetting
  40 \usepackage[pdftex,letterpaper,pdffitwindow=true,colorlinks=true,pdfpagemode=UseNone,
  41             bookmarks=true]{hyperref} % Hyperlinks for PDF versions
  42 \usepackage{hcolor}
  43 \slidepagestyle{fancy}
  44
  45 \slidesmag{4}     % Set magnification of slide
  46 \def\SeminarPaperWidth{\paperwidth / 2}
  47 \def\SeminarPaperHeight{\paperheight / 2}
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  49
  50
  51
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  56 %  \renewcommand{\sliderightmargin}{4mm}
  57   % To adjust the frame length to the header and footer ones
  58 %  \autoslidemarginstrue
  59   % We suppress the header and footer `fancyhdr' rules
  60 \fancyhf{} % Clear all fields
  61 \renewcommand{\headrule}{}
  62 \renewcommand{\footrule}{}
  63
  64 %  \usepackage{nohyperref}       % To deactivate the `hyperref' features
  65 %  \overlaysfalse                % To suppress overlays
  66 %  \def\special@paper{}% Needed to avoid `hyperref' to collapse with ``dvips''
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  98 \renewcommand{\labelitemi}{\footnotesize$\blacktriangleright$}
  99 \renewcommand{\labelitemii}{\footnotesize$\pmb\vartriangleright$}
 100 \renewcommand{\labelitemiii}{$\pmb\rightsquigarrow$}
 101 \begin{document}
 102 \begin{slide}
 103 \begin{center}
 104 \ParagraphTitle{\bf \Large Complete Translation of}
 105 \vspace{5mm} \
 106 {\bf \Large Unsafe Native Code to Safe Bytecode} \\
 107 \vspace{5mm} \
 108 \textit{Brian Alliet, RIT\\Adam Megacz, UC Berkeley} \
 109 \end{center}
 110 \end{slide}
 111
 112 \centerslidesfalse
 113
 114
 115 \begin{slide}\raggedright
 116 \renewcommand{\leftmargini}{5mm}
 117 {\Large{\textcolor{black}{The Problem: Specifics}}}
 118 \\\rule{\textwidth}{0.1pt}\\
 119
 120 \begin{itemize}
 121
 122
 123 \item
 124      XWT project (pure Java)
 125
 126 \item
 127      It requires:
 128 \begin{itemize}
 129
 130
 131 \item
 132          TrueType font rasterization
 133
 134 \item
 135          {\texttt{.cab}} extraction
 136
 137 \item
 138          JPEG {\it{decoding}}
 139
 140
 141 \end{itemize}
 142
 143 \end{itemize}
 144
 145
 146 \end{slide}
 147
 148
 149 \begin{slide}\raggedright
 150 \renewcommand{\leftmargini}{5mm}
 151 {\Large{\textcolor{black}{The Problem: Generally}}}
 152 \\\rule{\textwidth}{0.1pt}\\
 153
 154 \begin{itemize}
 155
 156
 157 \item
 158      Lots of high-quality, complex, code out there in unsafe
 159       languages
 160 \begin{itemize}
 161
 162
 163 \item
 164          \TeX
 165
 166 \item
 167          FreeType
 168
 169 \item
 170          {\texttt{libjpeg}}
 171
 172 \item
 173          {\texttt{gcc}}
 174 \end{itemize}
 175
 176
 177 \item
 178      Need to integrate with Java code
 179
 180 \item
 181      JNI isn't always an option
 182 \begin{itemize}
 183
 184
 185 \item
 186          Security
 187
 188 \item
 189          Portability
 190
 191
 192 \end{itemize}
 193
 194 \end{itemize}
 195
 196
 197 \end{slide}
 198
 199
 200 \begin{slide}\raggedright
 201 \renewcommand{\leftmargini}{5mm}
 202 {\Large{\textcolor{black}{Existing Approaches: Source-to-Source}}}
 203 \\\rule{\textwidth}{0.1pt}\\
 204
 205 \begin{itemize}
 206
 207 \item \begin{figure}[H]
 208 \begin{center}
 209 \epsfig{file=source-to-source,width=\textwidth-1in}
 210 \end{center}
 211 \end{figure}
 212
 213 \end{itemize}
 214
 215
 216 \end{slide}
 217
 218
 219 \begin{slide}\raggedright
 220 \renewcommand{\leftmargini}{5mm}
 221 {\Large{\textcolor{black}{Existing Approaches: Source-to-Source}}}
 222 \\\rule{\textwidth}{0.1pt}\\
 223
 224 \begin{itemize}
 225
 226
 227 \item
 228          Human-assisted:
 229 \begin{itemize}
 230
 231
 232 \item
 233              Jazillian
 234
 235 \item
 236              MoHCA-Java
 237 \end{itemize}
 238
 239
 240 \item
 241          Partial domain
 242 \begin{itemize}
 243
 244
 245 \item
 246              {\texttt{c2j}}
 247
 248 \item
 249              {\texttt{c2j++}}
 250
 251
 252 \end{itemize}
 253
 254 \end{itemize}
 255
 256
 257 \end{slide}
 258
 259
 260 \begin{slide}\raggedright
 261 \renewcommand{\leftmargini}{5mm}
 262 {\Large{\textcolor{black}{Existing Approaches: Source-to-Binary}}}
 263 \\\rule{\textwidth}{0.1pt}\\
 264
 265 \begin{itemize}
 266
 267 \item \begin{figure}[H]
 268 \begin{center}
 269 \epsfig{file=source-to-binary,width=\textwidth-1in}
 270 \end{center}
 271 \end{figure}
 272
 273 \end{itemize}
 274
 275
 276 \end{slide}
 277
 278
 279 \begin{slide}\raggedright
 280 \renewcommand{\leftmargini}{5mm}
 281 {\Large{\textcolor{black}{Existing Approaches: Source-to-Binary}}}
 282 \\\rule{\textwidth}{0.1pt}\\
 283
 284 \begin{itemize}
 285
 286
 287 \item
 288          {\texttt{egcs-jvm}}
 289
 290 \item
 291          lcc backend
 292
 293
 294 \end{itemize}
 295
 296
 297 \end{slide}
 298
 299
 300 \begin{slide}\raggedright
 301 \renewcommand{\leftmargini}{5mm}
 302 {\Large{\textcolor{black}{NestedVM: Binary-to-Source}}}
 303 \\\rule{\textwidth}{0.1pt}\\
 304
 305 \begin{itemize}
 306
 307 \item \begin{figure}[H]
 308 \begin{center}
 309 \epsfig{file=binary-to-source,width=\textwidth-1in}
 310 \end{center}
 311 \end{figure}
 312
 313 \end{itemize}
 314
 315
 316 \end{slide}
 317
 318
 319 \begin{slide}\raggedright
 320 \renewcommand{\leftmargini}{5mm}
 321 {\Large{\textcolor{black}{Advantages}}}
 322 \\\rule{\textwidth}{0.1pt}\\
 323
 324 \begin{itemize}
 325
 326
 327 \item
 328          No modifications to build process
 329
 330 \item
 331          Language-agnostic
 332
 333 \item
 334          Bug-for-bug compiler compatability
 335
 336 \item
 337          Zero post-translation human intervention
 338
 339
 340 \end{itemize}
 341
 342
 343 \end{slide}
 344
 345
 346 \begin{slide}\raggedright
 347 \renewcommand{\leftmargini}{5mm}
 348 {\Large{\textcolor{black}{Why MIPS?}}}
 349 \\\rule{\textwidth}{0.1pt}\\
 350
 351 \begin{itemize}
 352
 353
 354 \item
 355          Simple, clean, regular semantics
 356
 357 \item
 358          Well-defined ABI (caller save, callee save)
 359
 360 \item
 361          Many similarities to JVM
 362 \begin{itemize}
 363
 364
 365 \item
 366              32-bit aligned memory access
 367
 368 \item
 369              32x32 => 64bit multiply and divide
 370
 371 \item
 372              Unsigned math is rare
 373
 374 \item
 375              Easy to determine likely jump targets
 376
 377
 378 \end{itemize}
 379
 380 \end{itemize}
 381
 382
 383 \end{slide}
 384
 385
 386 \begin{slide}\raggedright
 387 \renewcommand{\leftmargini}{5mm}
 388 {\Large{\textcolor{black}{Memory Representation}}}
 389 \\\rule{\textwidth}{0.1pt}\\
 390
 391 \begin{itemize}
 392
 393 \item \begin{figure}[H]
 394 \begin{center}
 395 \epsfig{file=memory,width=\textwidth-1in}
 396 \end{center}
 397 \end{figure}
 398
 399 \end{itemize}
 400
 401
 402 \end{slide}
 403
 404
 405 \begin{slide}\raggedright
 406 \renewcommand{\leftmargini}{5mm}
 407 {\Large{\textcolor{black}{Code Representation}}}
 408 \\\rule{\textwidth}{0.1pt}\\
 409
 410 \begin{itemize}
 411
 412 \item \vspace{5mm}
 413
 414
 415
 416 \begin{Verbatim}[fontsize=\tiny,frame=single,rulecolor=\color{CodeBorder},resetmargins=true,gobble=0]
 417 private final static int r0 = 0;
 418 private int r1, r2, r3, /* ... */ r30;
 419 private int r31 = 0xdeadbeef;
 420
 421 public void run() {
 422     while (true)
 423         switch(pc) {
 424             case 0x10000: r29 = r29 - 32;
 425             case 0x10004: r1 = r4 + r5;
 426             case 0x10008: if (r1 == r6) {
 427                             /* delay slot */
 428                             r1 = r1 + 1;
 429                             pc = 0x10018:
 430                             continue; }
 431             case 0x1000C: r1 = r1 + 1;
 432             case 0x10010: r31 = 0x10018;
 433                           pc = 0x10210;
 434                           continue;
 435             case 0x10014: /* nop */
 436             case 0x10018: pc = r31; continue;
 437 \end{Verbatim}
 438
 439
 440 \end{itemize}
 441
 442
 443 \end{slide}
 444
 445
 446 \begin{slide}\raggedright
 447 \renewcommand{\leftmargini}{5mm}
 448 {\Large{\textcolor{black}{Trampoline Insertion}}}
 449 \\\rule{\textwidth}{0.1pt}\\
 450
 451 \begin{itemize}
 452
 453 \item \vspace{5mm}
 454
 455
 456
 457 \begin{Verbatim}[fontsize=\tiny,frame=single,rulecolor=\color{CodeBorder},resetmargins=true,gobble=0]
 458 public void run_0x10000() {
 459     while (true) switch(pc) {
 460         case 0x10000: ...
 461         case 0x10004: ...
 462         case 0x10010: r31 = 0x10018;
 463                       pc = 0x10210;
 464                       continue;
 465 ....
 466
 467 pubic void run_0x10200() {
 468     while (true) switch(pc) {
 469         case 0x10200: ...
 470         case 0x10204: ...
 471 ....
 472
 473 public void trampoline() {
 474     while (true) switch(pc&0xfffffe00) {
 475         case 0x10000:    run_0x10000(); break;
 476         case 0x10200:    run_0x10200(); break;
 477         case 0xdeadbe00: ...
 478 \end{Verbatim}
 479
 480
 481 \end{itemize}
 482
 483
 484 \end{slide}
 485
 486
 487 \begin{slide}\raggedright
 488 \renewcommand{\leftmargini}{5mm}
 489 {\Large{\textcolor{black}{Binary-to-Binary Translation}}}
 490 \\\rule{\textwidth}{0.1pt}\\
 491
 492 \begin{itemize}
 493
 494 \item \begin{figure}[H]
 495 \begin{center}
 496 \epsfig{file=binary-to-binary,width=\textwidth-1in}
 497 \end{center}
 498 \end{figure}
 499
 500 \end{itemize}
 501
 502
 503 \end{slide}
 504
 505
 506 \begin{slide}\raggedright
 507 \renewcommand{\leftmargini}{5mm}
 508 {\Large{\textcolor{black}{Binary-to-Binary Translation}}}
 509 \\\rule{\textwidth}{0.1pt}\\
 510
 511 \begin{itemize}
 512
 513
 514 \item
 515          Allows the use of more optimal bytecode sequences that cannot be expressed
 516           in java source
 517
 518 \item
 519          Smaller Bytecode - Javac doesn't emit space efficient bytecode
 520
 521 \item
 522          Translation is Much faster - doesn't need to go though the extra java
 523           source compilation step
 524
 525 \item
 526          Compiled code can be loaded into the JVM at Runtime.
 527
 528
 529 \end{itemize}
 530
 531
 532 \end{slide}
 533
 534
 535 \begin{slide}\raggedright
 536 \renewcommand{\leftmargini}{5mm}
 537 {\Large{\textcolor{black}{Binary-to-Binary: Performance}}}
 538 \\\rule{\textwidth}{0.1pt}\\
 539
 540 \begin{itemize}
 541
 542 \item \begin{figure}[H]
 543 \begin{center}
 544 \epsfig{file=chart7,width=\textwidth-1in}
 545 \end{center}
 546 \end{figure}
 547
 548 \end{itemize}
 549
 550
 551 \end{slide}
 552
 553
 554 \begin{slide}\raggedright
 555 \renewcommand{\leftmargini}{5mm}
 556 {\Large{\textcolor{black}{Binary-to-Binary: Performance}}}
 557 \\\rule{\textwidth}{0.1pt}\\
 558
 559 \begin{itemize}
 560
 561
 562 \item
 563         Performance increased from 10-30\%  after compiling to bytecode
 564          directly
 565
 566 \item
 567         Increase was primarily the result of two things
 568 \begin{itemize}
 569
 570
 571 \item
 572             More optimal handing of branch instructions
 573
 574 \item
 575             Use if the JVM stack in favor of temporary variables
 576
 577
 578 \end{itemize}
 579
 580 \end{itemize}
 581
 582
 583 \end{slide}
 584
 585
 586 \begin{slide}\raggedright
 587 \renewcommand{\leftmargini}{5mm}
 588 {\Large{\textcolor{black}{Optimizations: Optimal Method Size}}}
 589 \\\rule{\textwidth}{0.1pt}\\
 590
 591 \begin{itemize}
 592
 593 \item \begin{figure}[H]
 594 \begin{center}
 595 \epsfig{file=chart6,width=\textwidth-1in}
 596 \end{center}
 597 \end{figure}
 598
 599 \end{itemize}
 600
 601
 602 \end{slide}
 603
 604
 605 \begin{slide}\raggedright
 606 \renewcommand{\leftmargini}{5mm}
 607 {\Large{\textcolor{black}{Optimizations: Optimal Method Size}}}
 608 \\\rule{\textwidth}{0.1pt}\\
 609
 610 \begin{itemize}
 611
 612 \item \begin{figure}[H]
 613 \begin{center}
 614 \epsfig{file=chart5,width=\textwidth-1in}
 615 \end{center}
 616 \end{figure}
 617
 618 \end{itemize}
 619
 620
 621 \end{slide}
 622
 623
 624 \begin{slide}\raggedright
 625 \renewcommand{\leftmargini}{5mm}
 626 {\Large{\textcolor{black}{Better Branching}}}
 627 \\\rule{\textwidth}{0.1pt}\\
 628
 629 \begin{itemize}
 630
 631 \item \vspace{5mm}
 632
 633
 634
 635 \begin{Verbatim}[fontsize=\tiny,frame=single,rulecolor=\color{CodeBorder},resetmargins=true,gobble=0]
 636 // Java soucecode
 637 for(;;) {
 638     switch(pc) {
 639         case 0x10000: ...
 640         case 0x10004: // JMP 0x10000
 641             pc = 0x10000;
 642             continue
 643 \end{Verbatim}
 644
 645
 646 \end{itemize}
 647
 648
 649 \end{slide}
 650
 651
 652 \begin{slide}\raggedright
 653 \renewcommand{\leftmargini}{5mm}
 654 {\Large{\textcolor{black}{Better Branching}}}
 655 \\\rule{\textwidth}{0.1pt}\\
 656
 657 \begin{itemize}
 658
 659 \item \vspace{5mm}
 660
 661
 662
 663 \begin{Verbatim}[fontsize=\tiny,frame=single,rulecolor=\color{CodeBorder},resetmargins=true,gobble=0]
 664 // JVM Bytecode
 665 ...
 666 10: ...
 667 11: ...
 668 12: GOTO 10 // JMP 0x10000
 669 \end{Verbatim}
 670
 671
 672 \end{itemize}
 673
 674
 675 \end{slide}
 676
 677
 678 \begin{slide}\raggedright
 679 \renewcommand{\leftmargini}{5mm}
 680 {\Large{\textcolor{black}{Better Branching}}}
 681 \\\rule{\textwidth}{0.1pt}\\
 682
 683 \begin{itemize}
 684
 685
 686 \item
 687      Conditional branches were also not handled optimally in the Binary-
 688       to-source compiler
 689
 690
 691 \vspace{5mm}
 692
 693
 694
 695 \begin{Verbatim}[fontsize=\tiny,frame=single,rulecolor=\color{CodeBorder},resetmargins=true,gobble=0]
 696 if(condition) {
 697     pc = 0x10004;
 698     continue;
 699 }
 700 \end{Verbatim}
 701
 702
 703 \end{itemize}
 704
 705
 706 \end{slide}
 707
 708
 709 \begin{slide}\raggedright
 710 \renewcommand{\leftmargini}{5mm}
 711 {\Large{\textcolor{black}{Better Branching}}}
 712 \\\rule{\textwidth}{0.1pt}\\
 713
 714 \begin{itemize}
 715
 716
 717 \item
 718      Binary-to-binary compiler emits JVM branch instructions that
 719       branch directly to the destination
 720
 721
 722 \vspace{5mm}
 723
 724
 725
 726 \begin{Verbatim}[fontsize=\tiny,frame=single,rulecolor=\color{CodeBorder},resetmargins=true,gobble=0]
 727 ...
 728 10: ...
 729 11 ...
 730 12: IFEQ 10
 731 \end{Verbatim}
 732
 733
 734 \end{itemize}
 735
 736
 737 \end{slide}
 738
 739
 740 \begin{slide}\raggedright
 741 \renewcommand{\leftmargini}{5mm}
 742 {\Large{\textcolor{black}{More efficient delay slots}}}
 743 \\\rule{\textwidth}{0.1pt}\\
 744
 745 \begin{itemize}
 746
 747
 748 \item
 749      The MIPS ISA has ``delay slots'', that is, instruction after a branch instruction
 750       that are always executed even if the branch is taken.
 751
 752 \item
 753      The modification the delay slot makes to the registers used in the branch
 754       instruction cannot effect the branch. Therefore, the delay slot cannot just be
 755       output before the branch
 756
 757 \item
 758      In the binary-to-source compiler delay slots were simply output twice (once
 759       before setting the new pc and once after the branch)
 760
 761
 762 \end{itemize}
 763
 764
 765 \end{slide}
 766
 767
 768 \begin{slide}\raggedright
 769 \renewcommand{\leftmargini}{5mm}
 770 {\Large{\textcolor{black}{More efficient delay slots}}}
 771 \\\rule{\textwidth}{0.1pt}\\
 772
 773 \begin{itemize}
 774
 775
 776 \item
 777      The JVM stack can be used to eliminate this inefficiency.
 778
 779 \item
 780      The variables used in the comparison are pushed to the stack, the
 781       delay slot is executed, then the comparison/branch is done
 782
 783 \item
 784      Delay slot never needs to be output more than once
 785
 786
 787 \end{itemize}
 788
 789
 790 \end{slide}
 791
 792
 793 \begin{slide}\raggedright
 794 \renewcommand{\leftmargini}{5mm}
 795 {\Large{\textcolor{black}{Smaller Bytecode}}}
 796 \\\rule{\textwidth}{0.1pt}\\
 797
 798 \begin{itemize}
 799
 800
 801 \item
 802      Javac doesn't emit the most space efficient bytecode possible
 803
 804
 805 \vspace{5mm}
 806
 807
 808
 809 \begin{Verbatim}[fontsize=\tiny,frame=single,rulecolor=\color{CodeBorder},resetmargins=true,gobble=0]
 810 switch(pc >>> 8) {
 811 Case 0x1: run_0x100(); break;
 812 Case 0x2: run_0x200(); break;
 813 }
 814 \end{Verbatim}
 815
 816
 817
 818 \item
 819      Javac emits an ALOAD\_0 and an INVOKESPECIAL instruction for each case arm.
 820       The ALOAD\_0 can be hoisted out of the switch statement to create smaller bytecode.
 821
 822
 823
 824 \end{itemize}
 825
 826
 827 \end{slide}
 828
 829
 830 \begin{slide}\raggedright
 831 \renewcommand{\leftmargini}{5mm}
 832 {\Large{\textcolor{black}{Smaller Bytecode}}}
 833 \\\rule{\textwidth}{0.1pt}\\
 834
 835 \begin{itemize}
 836
 837
 838 \item
 839      Smaller bytecode also results from many of the performance
 840       increasing optimizations
 841
 842 \item
 843      He more efficient branch instructions also take up less space in bytecode
 844
 845 \item
 846      Using the stack in favor of local variables leads to less LOADs and
 847       STORESs
 848
 849 \item
 850      Better handling of delay slots avoids outputting each delay slot twice
 851
 852
 853 \end{itemize}
 854
 855
 856 \end{slide}
 857
 858
 859 \begin{slide}\raggedright
 860 \renewcommand{\leftmargini}{5mm}
 861 {\Large{\textcolor{black}{GCC Optimizations}}}
 862 \\\rule{\textwidth}{0.1pt}\\
 863
 864 \begin{itemize}
 865
 866
 867 \item
 868      NestedVM emulates a MIPS R2000 CPU but its performance profile
 869       is very different from the actual CPU.
 870
 871 \item
 872      GCC makes assumptions about the CPU that don't hold true for
 873       NestedVM
 874
 875 \item
 876      This leads to suboptimal code generation
 877
 878
 879 \end{itemize}
 880
 881
 882 \end{slide}
 883
 884
 885 \begin{slide}\raggedright
 886 \renewcommand{\leftmargini}{5mm}
 887 {\Large{\textcolor{black}{GCC Optimizations}}}
 888 \\\rule{\textwidth}{0.1pt}\\
 889
 890 \begin{itemize}
 891
 892
 893 \item
 894      Fortunately, GCC provides a wealth of options to compensate for
 895       this.
 896
 897 \item
 898      {\texttt{-falign-functions}} - Used to place functions on 512 byte boundaries to
 899       reduce the chances of a single function spanning several java
 900       methods
 901
 902
 903 \end{itemize}
 904
 905
 906 \end{slide}
 907
 908
 909 \begin{slide}\raggedright
 910 \renewcommand{\leftmargini}{5mm}
 911 {\Large{\textcolor{black}{GCC Optimizations}}}
 912 \\\rule{\textwidth}{0.1pt}\\
 913
 914 \begin{itemize}
 915
 916
 917 \item
 918      {\texttt{-fno-rename-registers}}
 919
 920 \item
 921      Normally GCC tries to use as many registers as possible make it easier to
 922       schedule code
 923
 924 \item
 925      This creates more work for the binary translator and the JVM. Using few
 926       registers simplifies the resulting bytecode and allows the JIT compiler to
 927       better optimize the resulting code.
 928
 929
 930 \end{itemize}
 931
 932
 933 \end{slide}
 934
 935
 936 \begin{slide}\raggedright
 937 \renewcommand{\leftmargini}{5mm}
 938 {\Large{\textcolor{black}{GCC Optimizations}}}
 939 \\\rule{\textwidth}{0.1pt}\\
 940
 941 \begin{itemize}
 942
 943
 944 \item
 945      {\texttt{-fno-schedule-insns}}
 946
 947 \item
 948      The results of some MIPS operations are not immediately available. Many
 949       instructions have delay slots that are executed before the results are
 950       available
 951
 952 \item
 953      GCC tries to take advantage of these delay slots by using them to do useful
 954       work
 955
 956 \item
 957      Since these results are immediately available in NestedVM this makes the
 958       code more complicated with no benefit.
 959
 960
 961 \end{itemize}
 962
 963
 964 \end{slide}
 965
 966
 967 \begin{slide}\raggedright
 968 \renewcommand{\leftmargini}{5mm}
 969 {\Large{\textcolor{black}{Impact of Optimizations}}}
 970 \\\rule{\textwidth}{0.1pt}\\
 971
 972 \begin{itemize}
 973
 974 \item \begin{figure}[H]
 975 \begin{center}
 976 \epsfig{file=chart4,width=\textwidth-1in}
 977 \end{center}
 978 \end{figure}
 979
 980 \end{itemize}
 981
 982
 983 \end{slide}
 984
 985
 986 \begin{slide}\raggedright
 987 \renewcommand{\leftmargini}{5mm}
 988 {\Large{\textcolor{black}{Overall Performance}}}
 989 \\\rule{\textwidth}{0.1pt}\\
 990
 991 \begin{itemize}
 992
 993 \item \begin{figure}[H]
 994 \begin{center}
 995 \epsfig{file=chart3,width=\textwidth-1in}
 996 \end{center}
 997 \end{figure}
 998
 999 \end{itemize}
1000
1001
1002 \end{slide}
1003
1004
1005 \begin{slide}\raggedright
1006 \renewcommand{\leftmargini}{5mm}
1007 {\Large{\textcolor{black}{Implementation}}}
1008 \\\rule{\textwidth}{0.1pt}\\
1009
1010 \begin{itemize}
1011
1012
1013 \item
1014          {\texttt{http://nestedvm.ibex.org/}}
1015
1016
1017
1018 \end{itemize}
1019
1020
1021 \end{slide}
1022 \end{document}