checkpoint

[sbp.git] / tests / scl.g

diff --git a/tests/scl.g b/tests/scl.g
new file mode 100644 (file)
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--- /dev/null
+++ b/tests/scl.g
@@ -0,0 +1,107 @@
+
+
+data foo = bar;
+type foo = bar;
+
+type Bit     = 0 | 1
+type Char    = Bit[16]
+type Boolean = true    | false
+type Int32   = Bit[32] | oob
+type Int64   = Bit[64] | oob
+type Pointer = Bit[64]
+type CodeBag = Pointer
+type Void   = token
+
+ship Adder3 (a b c -> d e f)
+  input e : !
+  ...
+
+  (x->a) => 3->b
+
+module latch32
+  input  data_in     : Int32
+  input  transparent : Boolean!
+  output data_out    : Int32
+  private
+    state keeper : Int32
+    data_out = keeper
+    transparent(true)  => keeper = data_in
+    transparent(false) => keeper = keeper
+
+module flipflop<T>
+   input  dataIn  : T
+   input  clock   : Void!
+   output dataOut : T
+   private
+      state keeper : T
+      data_out = keeper
+      clock() => keeper := 
+
+module join
+   input  in1 : Void!
+   input  in2 : Void!
+   output out : Void!
+   private
+
+A single-clock synchronous system is therefore a system with only a single variable of event type.  A synchronous sytem with mu
+
+
+// how do you specify the initial state of keeper nodes?  
+
+fleet
+  Adder3[1..3]
+
+
+Type   ::= Boolean
+
+
+
+Action  = Action ","  Action
+        | Value  "->" Port+
+        
+
+Identifier  ::=  Id  |  "(" Sym ")"
+
+Definition  ::=  Identifier "=" Body      /ws
+
+Grammar     ::=  
+
+clock
+random number generator
+register
+fifo
+compare
+
+clear-read port
+
+// positioning of elements on the screen (psuedo-comment?)
+// subcircuits
+// ports (in, out)
+
+Parameter   ::=  Identifier   (":" Type)?
+
+
+andgate {a b}->{c d} = 
+  input a, b
+  output c, d
+
+
+module fifo <in>
+  
+
+latch (input, hold) =
+  old = case 
+  out = case
+    
+
+
+and, xor, 2:1mux, 4:1mux
+
+leds, graphs, clock
+
+charing
+
+rs-latch
+dq-flipflop
+
+parameterization (?)