From 007fc55914bc4a48d9203b610457bfd5819107e1 Mon Sep 17 00:00:00 2001 From: adam Date: Fri, 6 Oct 2006 14:49:11 +0100 Subject: [PATCH] added atmel .apj file (used to generate bst) --- bitstreams/slipway.apj | 381 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 381 insertions(+) create mode 100644 bitstreams/slipway.apj diff --git a/bitstreams/slipway.apj b/bitstreams/slipway.apj new file mode 100644 index 0000000..3a73cae --- /dev/null +++ b/bitstreams/slipway.apj @@ -0,0 +1,381 @@ +Project(#fileName:->'V:\slipway\bitstreams\slipway.apj' #prjName:->'slipway.apj' #prjDir:->'v:\slipway\bitstreams' #parts:->PartList(#parts:->OrderedCollection(PartInstance(#name:->'U1' #part:-> +Part(#partCode:->'AT94K10-25DQC' #plugIn:->1.1 #properties:->PartProperties(#application:->'Commercial' #package:->'208PQFP' #productFamily:->'Atmel-FPSLIC' #architecture:->'Atmel-AT94K' #speedGrade:->'-25') #toolFlows:->ToolFlows( + ToolFlow(#name:->'Mentor-VHDL' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'VHDL File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assemble file') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl Files'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif file'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl file'))) + #windowsDescrAsText:->'VHDL Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl')) #imagesList:-> + ImagesList( + PartImage(#text:->'AT94K FPGA Core: The AT94K core contains array of 8-sided core cells which implements ultra fast design, without using any busing resources. This core is capable of implementing Cache logic and the inbuild FreeRAM can implements RAM without using logic resources.' #imageName:->'94k10.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection('Mentor-VHDL'-> + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl file'))) + #windowsDescrAsText:->'VHDL Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#true #toolBarIcon:->'' #visibleFromSymbol:->#false) 'Mentor-VHDL'-> + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif file'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#true #toolBarIcon:->'' #visibleFromSymbol:->#true)) #topLeftX:->29 #topLeftY:->30 #rightBottomX:->196 #rightBottomY:->220 #toolBarGrName:->'') + PartImage(#text:->'FPGA West IOs: The west side IOs are 3.3v and 33 MHz PCI compliant. All IO pads are registered IOs and can be programmed indivitually.' #imageName:->'westio.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->0 #topLeftY:->30 #rightBottomX:->21 #rightBottomY:->259 #toolBarGrName:->'') + PartImage(#text:->'FPGA South IOs: The south side IOs are 3.3v and 33 MHz PCI compliant. All IO pads are registered IOs and can be programmed indivitually.' #imageName:->'southio.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->30 #topLeftY:->230 #rightBottomX:->220 #rightBottomY:->251 #toolBarGrName:->'') + PartImage(#text:->'FPGA North IOs: The north side IOs are 3.3v and 33 MHz PCI compliant. All IO pads are registered IOs and can be programmed indivitually.' #imageName:->'northio.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->30 #topLeftY:->0 #rightBottomX:->199 #rightBottomY:->21 #toolBarGrName:->'') + PartImage(#text:->'Dual port Data SRAM interface: This Data SRAM interface component define the interface between the FPGA Core and the data SRAM inside the AVR . The FPGA core can directly access the data SRAM without interrupting AVR microcontroller.' #imageName:->'sram.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->196 #topLeftY:->157 #rightBottomX:->224 #rightBottomY:->220 #toolBarGrName:->'') + PartImage(#text:->'AVR Interface: This AVR interface component define the interface between the AVR CPU and FPGA Core. The FPGA core can not directly interact with AVR and its peripheral, it has to use the AVR bus architecture to interact with them. ' #imageName:->'avrbus.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->196 #topLeftY:->30 #rightBottomX:->223 #rightBottomY:->97 #toolBarGrName:->'') + PartImage(#text:->'AVR CPU: The AVR CPU is a 8-bit RISC microcontroller and it can executes over 30 MIPS. The AVR data bus interfaces directly into the FPGA and treats the FPGA as a large I/O device and can program the FPGA on-the-fly to create Cache logic configuration.' #imageName:->'avrcpu.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->250 #topLeftY:->33 #rightBottomX:->290 #rightBottomY:->77 #toolBarGrName:->'') + PartImage(#text:->'UART1: AVR microcontroller has two programmable Serial Universal Asynchronous Receiver and Transmitter. These serial data ports are used to communicate with external serial input/output devices.' #imageName:->'uart1.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->300 #topLeftY:->35 #rightBottomX:->340 #rightBottomY:->77 #toolBarGrName:->'') + PartImage(#text:->'UART2: AVR microcontroller has two programmable Serial Universal Asynchronous Receiver and Transmitter(UART). These serial data ports are used to communicate with external serial input/output devices.' #imageName:->'uart2.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->350 #topLeftY:->35 #rightBottomX:->390 #rightBottomY:->77 #toolBarGrName:->'') + PartImage(#text:->'Two wire serial interface: AVR support Insdustry standard two-wire interface. This serial bus is a bi-directional two-wire serial communication bus and it will carry information between the ICs connected to them.' #imageName:->'i2c.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->400 #topLeftY:->35 #rightBottomX:->450 #rightBottomY:->77 #toolBarGrName:->'') + PartImage(#text:->'Program SRAM: This Program SRAM is used by the AVR RISC microcontroller for program instruction storage. During configuration download, the configuration logic load the program instructions in to this SRAM. The FPGA core user logic can not directly access this SRAM.' #imageName:->'progsram.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->251 #topLeftY:->107 #rightBottomX:->350 #rightBottomY:->150 #toolBarGrName:->'') + PartImage(#text:->'Timer/Counter2: The Timer/Counter2 is a 8-bit general purpose counter and it has its own prescaling timer. This counter can be reset by setting the corresponding control bits in the Special Functions IO register.' #imageName:->'count2.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->358 #topLeftY:->107 #rightBottomX:->400 #rightBottomY:->150 #toolBarGrName:->'') + PartImage(#text:->'WatchDog Timer: The WatchDog Timer is clocked from a separate on-chip oscillator which runs at 1MHz. The watchdog timer reset interval can be adjusted by controlling the watchdog Timer prescaler.' #imageName:->'wdog.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->408 #topLeftY:->107 #rightBottomX:->450 #rightBottomY:->150 #toolBarGrName:->'') + PartImage(#text:->'Data SRAM: This dual port data SRAM resides inside the AVR and it is used for data storage. The FPGA user logic can directly access this data SRAM without interrupting AVR bus. Both FPGA and AVR have full read and write access to this SRAM.' #imageName:->'dpram.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->250 #topLeftY:->180 #rightBottomX:->335 #rightBottomY:->222 #toolBarGrName:->'') + PartImage(#text:->'Timer/Counter0: The Timer/Counter0 is a 8-bit general purpose counter and it has its own prescaling timer. This counter can be reset by setting the corresponding control bits in the Special Functions IO register.' #imageName:->'count1.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->346 #topLeftY:->180 #rightBottomX:->388 #rightBottomY:->222 #toolBarGrName:->'') + PartImage(#text:->'Timer/Counter1: The Timer/Counter1 is a 16-bit general purpose counter and it has its own prescaling timer. This counter can be reset by setting the corresponding control bits in the Special Functions IO register.' #imageName:->'count3.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->396 #topLeftY:->180 #rightBottomX:->448 #rightBottomY:->222 #toolBarGrName:->'') + PartImage(#text:->'Port D: Port D is an 8-bit parallel bidirectional IO port.' #imageName:->'portd.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->473 #topLeftY:->33 #rightBottomX:->503 #rightBottomY:->95 #toolBarGrName:->'') + PartImage(#text:->'Port E: Port E is an 8-bit parallel bidirectional IO port.' #imageName:->'porte.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->473 #topLeftY:->113 #rightBottomX:->503 #rightBottomY:->175 #toolBarGrName:->'') + PartImage(#text:->'bus1' #imageName:->'bus1.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->221 #topLeftY:->33 #rightBottomX:->250 #rightBottomY:->235 #toolBarGrName:->'') + PartImage(#text:->'bus2' #imageName:->'bus2.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->250 #topLeftY:->77 #rightBottomX:->450 #rightBottomY:->110 #toolBarGrName:->'') + PartImage(#text:->'bus3' #imageName:->'bus3.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->250 #topLeftY:->162 #rightBottomX:->450 #rightBottomY:->182 #toolBarGrName:->'') + PartImage(#text:->'bus4' #imageName:->'bus4.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->450 #topLeftY:->42 #rightBottomX:->480 #rightBottomY:->183 #toolBarGrName:->''))) #tools:->OrderedCollection(ToolInstance(#name:->'AT94K Device Options' #tool:-> + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection()) ToolInstance(#name:->'HDL Synthesis' #tool:-> + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection(DesignFileInstance(#fileName:->'v:\slipway\bitstreams\stupid.v' #designFile:-> + DesignFile(#path:->'v:\slipway\bitstreams\' #ext:->'v' #descriptionToText:->'Verilog File')))) ToolInstance(#name:->'Software Compiler' #tool:-> + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection()) ToolInstance(#name:->'AVR-FPGA Interface' #tool:-> + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection()) ToolInstance(#name:->'Pre-layout Coverification' #tool:-> + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection(DesignFileInstance(#fileName:->'v:\slipway\bitstreams\stupid_pretb.v' #designFile:-> + DesignFile(#path:->'v:\slipway\bitstreams\' #ext:->'v' #descriptionToText:->'')))) ToolInstance(#name:->'FPGA Place and Router' #tool:-> + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'stupid' #designFiles:->OrderedCollection(DesignFileInstance(#fileName:->'v:\slipway\bitstreams\stupid.edf' #designFile:-> + DesignFile(#path:->'v:\slipway\bitstreams\' #ext:->'edf' #descriptionToText:->'')))) ToolInstance(#name:->'Post-layout Coverification' #tool:-> + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'stupid' #designFiles:->OrderedCollection()) ToolInstance(#name:->'HDL Simulator - ModelSim' #tool:-> + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection()) ToolInstance(#name:->'Software Debugger' #tool:-> + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) #toolFlow:-> + ToolFlow(#name:->'Mentor-Verilog' #tools:->List( + Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List()) + #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files') + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File'))) + #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File'))) + #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) + Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file'))) + #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) + Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List( + DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files'))) + #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection())) #version:->1.1 #properties:->Dictionary(#FREQ->2 #B19->false #B4->false #SRAMWRITE->false #COMMANDFILENAME->'' #TESTBENCHFILE->'v:\stupid\stupid_pretb.v' #B18->false #USERLIBRARYLIST->List('v:\stupid\user94k.lib') #FPGABITSTREAM->false #FPGABITSTREAMNAME->'v:\stupid\stupid.bst' #B20->false #B30->true #LOADDATARAM->false #AVRPORTEDRIVE->1 #B16->false #COMBINEDBITSTREAMFILENAME->'v:\slipway\build\slipway_drone_complete.bst' #DATARAMFILETYPE->'Atmel Text Format' #B31->true #EXTINT3->1 #UART1PINS->1 #PROTECTAVRPROGRAMSRAM->false #GCK6SOURCE->#avr #AVRHEXFILE->true #OPENTYPE->#EDIF #B17->false #AVRRESETPINDISABLE->true #EXTINT1->1 #FGDFILENAME->'' #B25->false #AVRHEXFILENAME->'v:\slipway\build\slipway_drone.hex' #EDIFFILENAME->'V:\stupid\stupid.edf' #UART0PINS->0 #TOSCPADBIASRESISTOR->false #EXTINT2->1 #CACHEWRITE->true #EXECUTECOMMANDFILE->false #DENSITY->'1M' #PROGRAMSIZE->16 #XTALPADBIASRESISTOR->true #B2->true #B6->false #AVRPORTDDRIVE->1 #GENERATETESTBENCH->true #XTAL2PAD->false #B24->false #CPS->false #JTAG->true #B13->false #USERDEFINEDFILENAME->'' #EXTINT0->1 #PROTECTAVRBOOTBLOCK->false #B27->true #B3->false #B26->true #B21->false))))) \ No newline at end of file -- 1.7.10.4