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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
71 & \color{red} Distinguish {\tt Z}-flag from OLC=0\\
72 & \color{red} Add {\tt flush} instruction\\
73 & \color{red} Change {\t I} bit from ``Interruptable'' to ``Immune''\\
75 & Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\
77 & Note that decision to requeue is based on value of OLC {\it before} execution\\
78 & Note that decision to open the hatch is based on value of {\tt OS} bit\\
80 & Added {\tt OLC=0} predicate \\
81 & Eliminated {\tt TAPL} (made possible by previous change) \\
82 & Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\
84 & Fixed a few typos \\
85 & Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\
86 & Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\
88 & When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
89 & Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
91 & Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
92 & Reworked encoding of {\tt set} instruction \\
95 & Factored in Russell Kao's comments (thanks!)\\
96 & Added mechanism for setting C-flag from fabric even on outboxes\\
98 %& Made {\tt OLC} test a predicate-controlled condition\\
99 %& Rewrote ``on deck'' section \\
100 %& Added ``{\tt unset}'' value for {\tt ILC}\\
101 %& Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
104 %& added comment about address-to-path ship \\
105 %& changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
106 %& changed the order of instructions in the encoding map \\
108 %& added epilogue fifo to diagrams \\
109 %& indicated that a token sent to the instruction port is treated as a torpedo \\
111 %& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
112 %& replaced {\tt literal} with {\tt shift} instruction \\
114 %& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
115 %& Removed ability to manually set the {\tt C} flag \\
116 %& Expanded predicate field to three bits \\
117 %& New literals scheme (via shifting) \\
118 %& Instruction encoding changes made at Ivan's request (for layout purposes) \\
119 %& Added summary of instruction encodings on last page \\
121 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
123 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
124 %& update table 3.1.2 \\
125 %& rename {\tt S} flag to {\tt C} \\
126 %& noted that {\tt setFlags} can be used as {\tt nop} \\
128 %& removed the {\tt L} flag (epilogues can now do this) \\
129 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
130 %& renamed {\tt data} instruction to {\tt literal} \\
131 %& renamed {\tt send} instruction to {\tt move} \\
133 %& added ``if its predicate is true'' to repeat count \\
134 %& added note that red wires do not contact ships \\
135 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
136 %& removed black dot from diagrams \\
137 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
138 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
139 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
140 %& added section ``Torpedo Details'' \\
141 %& removed {\tt torpedo} instruction \\
144 %& renamed loop+repeat to outer+inner (not in red) \\
145 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
146 %& rewrote ``inner and outer loops'' section \\
147 %& updated all diagrams \\
150 %& Moved address bits to the LSB-side of a 37-bit instruction \\
151 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
152 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
153 %& Created the {\tt Hold} field \\
154 %& Changed how ReLooping works \\
155 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
162 \epsfig{file=all,height=1.5in}
163 \epsfig{file=overview-new,height=1.5in}
168 \section{Overview of Fleet}
170 A Fleet processor is organized around a {\it switch fabric}, which is
171 a packet-switched network with reliable in-order delivery. The switch
172 fabric is used to carry data between different functional units,
173 called {\it ships}. Each ship is connected to the switch fabric by
174 one or more programmable elements known as {\it docks}.
176 A {\it path} specifies a route through the switch fabric from a
177 particular {\it source} to a particular {\it destination}. The
178 combination of a path and a single word to be delivered is called a
179 {\it packet}. The switch fabric carries packets from their sources to
180 their destinations. Each dock has two destinations: one for {\it
181 instructions} and one for {\it data}. A Fleet is programmed by
182 depositing instruction packets into the switch fabric with paths that
183 will lead them to instruction destinations of the docks at which they
186 When a packet arrives at the instruction destination of a dock, it is
187 enqueued for execution. Before the instruction executes, it may cause
188 the dock to wait for a packet to arrive at the dock's data destination
189 or for a value to be presented by the ship. When an instruction
190 executes it may consume this data and may present a data value to the
191 ship or transmit a packet.
193 When an instruction sends a packet into the switch fabric, it may
194 specify that the payload of the packet is irrelevant. Such packets
195 are known as {\it tokens}, and consume less energy than data packets.
199 \epsfig{file=overview-new,width=2.5in}\\
200 {\it Overview of a Fleet processor; dark gray shading represents the
201 switch fabric, ships are shown in light gray, and docks are shown in blue.}
207 \section{The FleetTwo Dock}
209 The diagram below represents a conceptual view of the interface
210 between ships and the switch fabric; actual implementation circuitry
214 \epsfig{file=all,width=3.5in}\\
215 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
216 blue lines carry either tokens or data words, red lines carry either
217 instructions or torpedoes, and dashed lines carry only tokens.}
220 Each dock consists of a {\it data latch}, which is as wide as a single
221 machine word and a {\it pump}, which is a circular fifo of
222 instruction-width latches. The values in the pump control the data
223 latch. The dock also includes a {\it path latch}, which
224 stores the path along which outgoing packets will be sent.\color{black}
226 Note that the pump in each dock has a destination of its own; this is
227 the {\it instruction destination} mentioned in the previous section.
229 From any source to any dock's data destination there are
230 two distinct paths which differ by a single bit. This bit is known as
231 the ``signal'' bit, and the routing of a packet is not affected by it;
232 the signal bit is used to pass control values between docks. Note that paths
233 terminating at an {\it instruction} destination need not have a signal
237 \section{Instructions}
239 In order to cause an instruction to execute, the programmer must first
240 arrange for that instruction word to arrive in the data latch of some
241 output dock. For example, this might be the ``data read'' output dock
242 of the memory access ship or the output of a fifo ship. Once an
243 instruction has arrived at this output dock, it is {\it dispatched} by
244 sending it to the {\it instruction port} of the dock at which it is to
247 Each instruction is 26 bits long, which makes it possible for an
248 instruction and an 11-bit path to fit in a single word of memory.
249 This path is the path from the {\it dispatching} dock to the {\it
252 \setlength{\bitwidth}{3.5mm}
254 \begin{bytefield}{37}
255 \bitheader[b]{0,10,11,36}\\
256 \bitbox{26}{instruction}
257 \bitbox{11}{dispatch path}
263 \subsection{Life Cycle of an Instruction}
265 The diagram below shows an input dock for purposes of illustration:
268 \epsfig{file=in,width=4in}\\
272 %\subsection{The Hatch}
276 %Note the mux on the path between {\tt EF} (epilogue fifo) and {\tt IF}
277 %(instruction fifo); this is known as ``the hatch''. The exact
278 %behavior of the hatch is documented in
279 %\href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50};
280 %a summary of its behavior is included below.
282 %When an instruction arrives at the epilogue fifo ({\tt EF}), it waits
283 %there until the hatch is in the unsealed state; the instruction then
284 %enters the instruction fifo. When an instruction emerges from the
285 %instruction fifo, it arrives at the ``on deck'' ({\tt OD}) stage,
286 %where it may execute.
290 \epsfig{file=out,width=4in}\\
294 \subsubsection{Torpedoes}
296 A token sent to an instruction destination is called a {\it torpedo}.
297 When a torpedo arrives at the tail of {\tt EF}, it is deposited in a
298 waiting area (not shown) rather than being enqueued into {\tt EF}.
300 \subsection{Format of an Instruction}
302 All instruction words have the following format:
304 \newcommand{\bitsHeader}{
309 \newcommand{\bitsHeaderNoI}{
315 \setlength{\bitwidth}{3.5mm}
317 \begin{bytefield}{37}
318 \bitheader[b]{0,10,11,31,32,34-36}\\
323 \bitbox{11}{dispatch path}
329 \item The {\tt I} bit stands for \color{red}{\tt Immune}\color{black},
330 and indicates if an instruction is
331 \color{red}immune\color{black}\ to torpedoes. This bit only appears
332 in {\tt move} instructions.
334 \item The {\tt OS} (``One Shot'') bit indicates whether or not this
335 instruction can pass through the pump more than once. If set to
336 {\tt 1}, then the instruction is a ``one-shot'' instruction, and
337 does not pass through the instruction fifo more than once.
339 \item The {\tt P} bits are a {\it predicate}; this
340 holds a code which indicates if the instruction should be executed or
341 ignored depending on the state of flags in the dock.
345 \subsection{Loop Counters}
347 A programmer can perform two types of loops: {\it inner} loops of only
348 one instruction and {\it outer} loops of multiple instructions. Inner
349 loops may be nested within an outer loop, but no other nesting of
352 The dock has two loop counters, one for each kind of loop:
355 \item {\tt OLC} is the Outer Loop Counter
356 \item {\tt ILC} is the Inner Loop Counter
359 The {\tt OLC} applies to all instructions and can hold integers {\tt
362 The {\tt ILC} applies only to {\tt move} instructions and can hold
363 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
364 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
365 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
366 executes until interrupted by a torpedo. After every {\tt move}
367 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
368 to {\tt 1}, {\it not to 0}).
371 \subsection{Flags and Predication}
373 The pump has \color{red}four\color{black}\ flags: {\tt A}, {\tt B},
374 {\tt C}, \color{red}and {\tt Z}\color{black}.
377 \item The {\tt A} and {\tt B} flags are general-purpose flags which
378 may be set and cleared by the programmer.
382 % The {\tt L} flag, known as the {\it last} flag, is set whenever
383 % the value in the outer counter ({\tt OLC}) is one,
386 % that the dock is in the midst of the last iteration of an
387 % outer loop. This flag can be used to perform certain
388 % operations (such as sending a completion token) only on the last
389 % iteration of an outer loop.
391 \item The {\tt C} flag is known as the {\it control} flag, and may be
392 set by the {\tt move} instruction based on information from the
393 ship or from an inbound packet. See the {\tt move} instruction
398 \item The {\tt Z} flag is known as the {\it zero} flag; it is set
399 whenever the {\tt OLC} is {\it decremented to zero} or a torpedo strikes, and is cleared
400 whenever the {\tt OLC} is loaded. Note that loading the {\tt OLC}
401 with zero will actually {\it clear} the {\tt Z} flag.
407 The {\tt P} field specifies a three-bit {\it predicate}. The
408 predicate determines which conditions must be true in order for the
409 instruction to execute; if it is not executed, it is simply {\it
410 ignored}. The table below shows what conditions must be true in
411 order for an instruction to execute:
414 \begin{tabular}{|r|l|}\hline
415 Code & Execute if \\\hline
416 {\tt 000:} & \color{red}{\tt Z=0}\color{black}\ and {\tt A=0} \\
417 {\tt 001:} & \color{red}{\tt Z=0}\color{black}\ and {\tt A=1} \\
418 {\tt 010:} & \color{red}{\tt Z=0}\color{black}\ and {\tt B=0} \\
419 {\tt 011:} & \color{red}{\tt Z=0}\color{black}\ and {\tt B=1} \\
420 {\tt 100:} & Unused \\
421 {\tt 101:} & \color{red}{\tt Z=1}\color{black}\ \\
422 {\tt 110:} & \color{red}{\tt Z=0}\color{black}\ \\
423 {\tt 111:} & always \\
428 \subsection{The Hatch}
430 What follows is a conservative approximation of the actual behavior of
432 For complete details on the behavior of the hatch, see
433 \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50}.
435 For the purposes of this section, instructions will be
436 classified into three categories: one-shot instructions ({\tt OS=1}),
437 requeueable instructions ({\tt OS=0}), and {\tt tail} instructions.
439 To avoid deadlock, the programmer must ensure that:
443 \item A requeueable instruction is never followed immediately by a
446 \item A one-shot instruction is never followed immediately by a {\tt
449 \item No contiguous sequence of requeueable instructions is longer
450 than the length of the instruction fifo.
452 \item If a requeueable instruction is preceded by a one-shot
453 instruction or a {\tt tail}, then it must be the case that
454 \color{red}{\tt Z=0}\color{black}\ both before and after the first
455 time that instruction executes.
457 \item If \color{red}{\tt Z=1}\color{black}, only a one-shot instruction may set it to a
462 The dock guarantees that:
466 \item If a requeueable instruction is preceded by a one-shot
467 instruction or a {\tt tail}, then the {\it following}
468 instruction will not execute until a {\tt tail} has reached the
471 \item Once a {\tt tail} instruction reaches the hatch, no further
472 instructions will be enqueued until a requeueable instruction
473 reaches the execution stage and \color{red}{\tt Z=1}\color{black}.
481 When an instruction arrives on deck, two concurrent processes are
486 \item If the instruction on deck is a requeueable instruction
487 ({\tt OS=0}) and \color{red}{\tt Z=0}\color{black}, a copy of
488 the instruction is requeued.
494 If the instruction's predicate condition is not met (see
495 section on predicates), do nothing.
498 {\it Otherwise} if the instruction is interruptible ({\tt I=\color{red}0\color{black}})
499 and a torpedo is present in the waiting area: consume the
500 torpedo, \color{red}set the {\tt Z} flag\color{black}\ and
501 set the inner loop counter to one ({\tt ILC=1}).
504 {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it
505 not} a {\tt move}: execute the instruction.
514 \section{Instructions}
516 The dock supports four instructions:
517 {\tt move} (variants: {\tt moveto}, {\tt dispatch}),
524 \subsection{{\tt move}}
526 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
528 \begin{bytefield}{26}
529 \bitheader[b]{14-20}\\
543 \begin{bytefield}{26}
544 \bitheader[b]{0,12,13}\\
545 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
548 \bitbox{13}{\tt Immediate}
551 \begin{bytefield}{26}
552 \bitheader[b]{11,12,13}\\
553 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:25]\to Path}})\ \ }
562 \begin{bytefield}{26}
563 \bitheader[b]{11,12,13}\\
564 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
575 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
576 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
577 \item {\tt Dc} - Data Capture: pulse the data latch.
578 \item {\tt Do} - Data Output: fill the data successor.
579 \item {\tt To} - Token Output: fill the token successor.
582 The data successor and token successor must both be empty in order for
583 a {\tt move} instruction to attempt execution.
585 Every time the {\tt move} instruction executes, the {\tt C} flag may
589 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
590 of the incoming packet if {\tt Di} or {\tt Ti} is set.
592 \item At an {\it output} dock the {\tt C} flag is set to a value
593 provided by the ship if the {\tt Di} bit is set, and to the
594 signal bit of the incoming packet if {\tt Di} is clear and {\tt
599 The {\tt flush} instruction is a variant of {\tt move} which is valid
600 only at input docks. It has the same effect as {\tt deliver}, except
601 that it sets a special ``flushing'' indicator along with the data
604 \newcommand{\bitsFlush}{\setlength{\bitwidth}{5mm}
607 \begin{bytefield}{26}
608 \bitheader[b]{14-18}\\
609 \bitbox[r]{7}{\raggedleft{\tt flush\ \ }}
623 When a ship fires, it must examine the ``flushing'' indicators on the
624 input docks whose fullness was part of the firing condition. If all
625 of the input docks' flushing indicators are set, the ship must drain
626 all of their data successors and take no action. If some, but not
627 all, of the indicators are set, the ship must drain {\it only the data
628 successors of the docks whose indicators were {\bf not} set}, and
629 take no action. If none of the flushing indicators was set, the ship
636 \subsection{{\tt set}}
638 The {\tt set} command is used to set or decrement the inner loop
639 counter, outer loop counter, and data latch.
641 \newcommand{\bitsSet}{
642 \setlength{\bitwidth}{5mm}
644 \begin{bytefield}{26}
645 \bitheader[b]{19-25}\\
655 \begin{bytefield}{26}
656 \bitheader[b]{0,5,12-18}\\
657 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
659 \bitbox{4}{\tt 1000\color{black}}
662 \bitbox{6}{\tt Immediate}
665 \begin{bytefield}{26}
666 \bitheader[b]{12-18}\\
667 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
669 \bitbox{4}{\tt 1000\color{black}}
674 \begin{bytefield}{26}
675 \bitheader[b]{12-18}\\
676 \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
678 \bitbox{4}{\tt 1000\color{black}}
683 \begin{bytefield}{26}
684 \bitheader[b]{0,5,6,12-18}\\
685 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
687 \bitbox{4}{\tt 0100\color{black}}
691 \bitbox{6}{\tt Immediate}
694 \begin{bytefield}{26}
695 \bitheader[b]{6,12-18}\\
696 \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
698 \bitbox{4}{\tt 0100\color{black}}
705 \begin{bytefield}{26}
706 \bitheader[b]{12-18}\\
707 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
709 \bitbox{4}{\tt 0100\color{black}}
714 \begin{bytefield}{26}
715 \bitheader[b]{0,13-18}\\
716 \bitbox[1]{6}{\raggedleft \footnotesize {\tt X-Extended Immediate}\to{\tt Data Latch}}
718 \bitbox{4}{\tt 0010\color{black}}
720 \bitbox{14}{\tt Immediate}
723 \begin{bytefield}{26}
724 \bitheader[b]{0,5,6,11,15-18}\\
725 \bitbox[1]{6}{\raggedleft {\tt Update Flags}}
727 \bitbox{4}{\tt 0001\color{black}}
729 \bitbox{6}{\tt nextA}
730 \bitbox{6}{\tt nextB}
739 The FleetTwo implementation is likely to have an unarchitected
740 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
741 with the possibly-extended literal {\it at the time that the {\tt set}
742 instruction comes on deck}. This latch is then copied into the data
743 latch when a {\tt set Data Latch} instruction
744 executes\color{black}.
746 Each of the {\tt nextA} and {\tt nextB} fields has the following
747 structure, and indicates which old flag values should be logically
748 {\tt OR}ed together to produce the new flag value:
754 \bitbox{1}{${\text{\tt A}}$}
755 \bitbox{1}{$\overline{\text{\tt A}}$}
756 \bitbox{1}{${\text{\tt B}}$}
757 \bitbox{1}{$\overline{\text{\tt B}}$}
758 \bitbox{1}{${\text{{\tt C}\ }}$}
759 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
763 Each bit corresponds to one possible input; all inputs whose bits are
764 set are {\tt OR}ed together, and the resulting value is assigned to
765 the flag. Note that if none of the bits are set, the value assigned
766 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
767 OR}ing any flag with its complement, and that {\tt set Flags} can
768 be used to create a {\tt nop} (no-op) by setting each flag to itself.
774 \subsection{{\tt shift}}
776 \newcommand{\shiftImmediateSize}{19}
778 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
779 bits. When a {\tt shift} instruction is executed, this immediate is copied
780 into the least significant \shiftImmediateSize\ bits of the data latch,
781 and the remaining most significant bits of the data latch are loaded
782 with the value formerly in the least significant bits of the data latch.
783 In this manner, large literals can be built up by ``shifting'' them
784 into the data latch \shiftImmediateSize\ bits at a time.
786 \newcommand{\bitsShift}{
787 \setlength{\bitwidth}{5mm}
789 \begin{bytefield}{26}
790 \bitheader[b]{0,18-20}\\
797 \bitbox{\shiftImmediateSize}{Immediate}
802 The FleetTwo implementation is likely to have an unarchitected
803 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
804 with the literal {\it at the time that the {\tt shift} instruction
805 comes on deck}. This latch is then copied into the data latch when
806 the instruction executes.
810 \subsection{{\tt tail}}
812 \newcommand{\bitsTail}{
813 \setlength{\bitwidth}{5mm}
815 \begin{bytefield}{26}
816 \bitheader[b]{19-20}\\
827 When a {\tt tail} instruction reaches the hatch and the hatch is open,
828 it seals the hatch. The {\tt tail} instruction does not enter the
833 %\subsection{{\tt takeOuterLoopCounter}}
835 %\setlength{\bitwidth}{5mm}
837 %\begin{bytefield}{26}
838 % \bitheader[b]{16-19,21}\\
852 %This instruction copies the value in the outer loop counter {\tt OLC}
853 %into the least significant bits of the data latch and leaves all other
854 %bits of the data latch unchanged.
856 %\subsection{{\tt takeInnerLoopCounter}}
858 %\setlength{\bitwidth}{5mm}
860 %\begin{bytefield}{26}
861 % \bitheader[b]{16-19,21}\\
875 %This instruction copies the value in the inner loop counter {\tt ILC}
876 %into the least significant bits of the data latch and leaves all other
877 %bits of the data latch unchanged.
882 %%\subsection{{\tt interrupt}}
884 %%\setlength{\bitwidth}{5mm}
886 %\begin{bytefield}{26}
887 % \bitheader[b]{0,5,16-19,21}\\
898 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
899 %there for the {\tt OD} stage to be full with an instruction that has
900 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
901 %{\it will not execute}, but {\it may reloop} if the conditions for
903 %\footnote{The ability to interrupt an instruction yet have it reloop is very
904 %useful for processing chunks of data with a fixed size header and/or
905 %footer and a variable length body.}
908 %\subsection{{\tt massacre}}
910 %\setlength{\bitwidth}{5mm}
912 %\begin{bytefield}{26}
913 % \bitheader[b]{16-19,21}\\
925 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
926 %for the {\tt OD} stage to be full with an instruction that has the
927 %{\tt IM} bit set. When this occurs, all instructions in the
928 %instruction fifo (including {\tt OD}) are retired.
930 %\subsection{{\tt clog}}
932 %\setlength{\bitwidth}{5mm}
934 %\begin{bytefield}{26}
935 % \bitheader[b]{16-19,21}\\
947 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
948 %no more instructions will be executed until an {\tt unclog} is
951 %\subsection{{\tt unclog}}
953 %\setlength{\bitwidth}{5mm}
955 %\begin{bytefield}{26}
956 % \bitheader[b]{16-19,21}\\
962 % \bitbox[lrtb]{2}{11}
968 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
969 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
970 %instructions retire.
972 %Note that issuing an {\tt unclog} instruction to a dock which is not
973 %clogged and whose instruction fifo contains no {\tt clog} instructions
974 %will cause the dock to deadlock.
979 \section*{Instruction Encoding Map\color{black}}
981 \hspace{-1cm}{\tt shift}\\
984 \hspace{-1cm}{\tt set}\\
987 \hspace{-1cm}{\tt move}\\
993 \hspace{-1cm}{\tt tail}\\
1000 \epsfig{file=all,height=5in,angle=90}
1003 \subsection*{Input Dock}
1004 \epsfig{file=in,width=8in,angle=90}
1007 \subsection*{Output Dock}
1008 \epsfig{file=out,width=8in,angle=90}
1012 %\epsfig{file=ports,height=5in,angle=90}
1015 %\epsfig{file=best,height=5in,angle=90}