1 \documentclass[10pt]{article}
6 \usepackage{bytefield1}
18 \bibliographystyle{alpha}
19 \pagestyle{fancyplain}
21 \definecolor{light}{gray}{0.7}
23 \setlength{\marginparwidth}{1.2in}
24 \let\oldmarginpar\marginpar
25 \renewcommand\marginpar[1]{\-\oldmarginpar[\raggedleft\footnotesize #1]%
26 {\raggedright\footnotesize #1}}
29 \newcommand{\footnoteremember}[2]{
32 \setcounter{#1}{\value{footnote}}
33 } \newcommand{\footnoterecall}[1]{
34 \footnotemark[\value{#1}]
42 %\oddsidemargin 0.25in
43 %\evensidemargin 0.25in
45 \def\to{\ $\rightarrow$\ }
55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
70 & Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\
72 & Note that decision to requeue is based on value of OLC {\it before} execution\\
73 & Note that decision to open the hatch is based on value of {\tt OS} bit\\
75 & Added {\tt OLC=0} predicate \\
76 & Eliminated {\tt TAPL} (made possible by previous change) \\
77 & Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\
79 & Fixed a few typos \\
80 & Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\
81 & Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\
83 & When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
84 & Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
86 & Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
87 & Reworked encoding of {\tt set} instruction \\
90 & Factored in Russell Kao's comments (thanks!)\\
91 & Added mechanism for setting C-flag from fabric even on outboxes\\
93 & Made {\tt OLC} test a predicate-controlled condition\\
94 & Rewrote ``on deck'' section \\
95 & Added ``{\tt unset}'' value for {\tt ILC}\\
96 & Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
99 & added comment about address-to-path ship \\
100 & changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
101 & changed the order of instructions in the encoding map \\
103 & added epilogue fifo to diagrams \\
104 & indicated that a token sent to the instruction port is treated as a torpedo \\
106 %& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
107 %& replaced {\tt literal} with {\tt shift} instruction \\
109 %& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
110 %& Removed ability to manually set the {\tt C} flag \\
111 %& Expanded predicate field to three bits \\
112 %& New literals scheme (via shifting) \\
113 %& Instruction encoding changes made at Ivan's request (for layout purposes) \\
114 %& Added summary of instruction encodings on last page \\
116 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
118 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
119 %& update table 3.1.2 \\
120 %& rename {\tt S} flag to {\tt C} \\
121 %& noted that {\tt setFlags} can be used as {\tt nop} \\
123 %& removed the {\tt L} flag (epilogues can now do this) \\
124 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
125 %& renamed {\tt data} instruction to {\tt literal} \\
126 %& renamed {\tt send} instruction to {\tt move} \\
128 %& added ``if its predicate is true'' to repeat count \\
129 %& added note that red wires do not contact ships \\
130 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
131 %& removed black dot from diagrams \\
132 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
133 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
134 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
135 %& added section ``Torpedo Details'' \\
136 %& removed {\tt torpedo} instruction \\
139 %& renamed loop+repeat to outer+inner (not in red) \\
140 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
141 %& rewrote ``inner and outer loops'' section \\
142 %& updated all diagrams \\
145 %& Moved address bits to the LSB-side of a 37-bit instruction \\
146 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
147 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
148 %& Created the {\tt Hold} field \\
149 %& Changed how ReLooping works \\
150 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
157 \epsfig{file=all,height=1.5in}
158 \epsfig{file=overview-new,height=1.5in}
163 \section{Overview of Fleet}
165 A Fleet processor is organized around a {\it switch fabric}, which is
166 a packet-switched network with reliable in-order delivery. The switch
167 fabric is used to carry data between different functional units,
168 called {\it ships}. Each ship is connected to the switch fabric by
169 one or more programmable elements known as {\it docks}.
171 A {\it path} specifies a route through the switch fabric from a
172 particular {\it source} to a particular {\it destination}. The
173 combination of a path and a single word to be delivered is called a
174 {\it packet}. The switch fabric carries packets from their sources to
175 their destinations. Each dock has two destinations: one for {\it
176 instructions} and one for {\it data}. A Fleet is programmed by
177 depositing instruction packets into the switch fabric with paths that
178 will lead them to instruction destinations of the docks at which they
181 When a packet arrives at the instruction destination of a dock, it is
182 enqueued for execution. Before the instruction executes, it may cause
183 the dock to wait for a packet to arrive at the dock's data destination
184 or for a value to be presented by the ship. When an instruction
185 executes it may consume this data and may present a data value to the
186 ship or transmit a packet.
188 When an instruction sends a packet into the switch fabric, it may
189 specify that the payload of the packet is irrelevant. Such packets
190 are known as {\it tokens}, and consume less energy than data packets.
194 \epsfig{file=overview-new,width=2.5in}\\
195 {\it Overview of a Fleet processor; dark gray shading represents the
196 switch fabric, ships are shown in light gray, and docks are shown in blue.}
202 \section{The FleetTwo Dock}
204 The diagram below represents a conceptual view of the interface
205 between ships and the switch fabric; actual implementation circuitry
209 \epsfig{file=all,width=3.5in}\\
210 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
211 blue lines carry either tokens or data words, red lines carry either
212 instructions or torpedoes, and dashed lines carry only tokens.}
215 Each dock consists of a {\it data latch}, which is as wide as a single
216 machine word and a {\it pump}, which is a circular fifo of
217 instruction-width latches. The values in the pump control the data
218 latch. The dock also includes a {\it path latch}, which
219 stores the path along which outgoing packets will be sent.\color{black}
221 Note that the pump in each dock has a destination of its own; this is
222 the {\it instruction destination} mentioned in the previous section.
224 From any source to any dock's data destination there are
225 two distinct paths which differ by a single bit. This bit is known as
226 the ``signal'' bit, and the routing of a packet is not affected by it;
227 the signal bit is used to pass control values between docks. Note that paths
228 terminating at an {\it instruction} destination need not have a signal
232 \section{Instructions}
234 In order to cause an instruction to execute, the programmer must first
235 arrange for that instruction word to arrive in the data latch of some
236 output dock. For example, this might be the ``data read'' output dock
237 of the memory access ship or the output of a fifo ship. Once an
238 instruction has arrived at this output dock, it is {\it dispatched} by
239 sending it to the {\it instruction port} of the dock at which it is to
242 Each instruction is 26 bits long, which makes it possible for an
243 instruction and an 11-bit path to fit in a single word of memory.
244 This path is the path from the {\it dispatching} dock to the {\it
247 \setlength{\bitwidth}{3.5mm}
249 \begin{bytefield}{37}
250 \bitheader[b]{0,10,11,36}\\
251 \bitbox{26}{instruction}
252 \bitbox{11}{dispatch path}
258 \subsection{Life Cycle of an Instruction}
260 The diagram below shows an input dock for purposes of illustration:
263 \epsfig{file=in,width=4in}\\
267 %\subsection{The Hatch}
271 %Note the mux on the path between {\tt EF} (epilogue fifo) and {\tt IF}
272 %(instruction fifo); this is known as ``the hatch''. The exact
273 %behavior of the hatch is documented in
274 %\href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50};
275 %a summary of its behavior is included below.
277 %When an instruction arrives at the epilogue fifo ({\tt EF}), it waits
278 %there until the hatch is in the unsealed state; the instruction then
279 %enters the instruction fifo. When an instruction emerges from the
280 %instruction fifo, it arrives at the ``on deck'' ({\tt OD}) stage,
281 %where it may execute.
285 \epsfig{file=out,width=4in}\\
289 \subsubsection{Torpedoes}
291 A token sent to an instruction destination is called a {\it torpedo}.
292 When a torpedo arrives at the tail of {\tt EF}, it is deposited in a
293 waiting area (not shown) rather than being enqueued into {\tt EF}.
295 \subsection{Format of an Instruction}
297 All instruction words have the following format:
299 \newcommand{\bitsHeader}{
304 \newcommand{\bitsHeaderNoI}{
310 \setlength{\bitwidth}{3.5mm}
312 \begin{bytefield}{37}
313 \bitheader[b]{0,10,11,31,32,34-36}\\
318 \bitbox{11}{dispatch path}
323 \item The {\tt I} bit stands for {\tt Interruptible}, and indicates if an
324 instruction is vulnerable to torpedoes. This bit only appears in {\tt move} instructions.
326 \item The {\tt OS} (``One Shot'') bit indicates whether or not this
327 instruction can pass through the pump more than once. If set to
328 {\tt 1}, then the instruction is a ``one-shot'' instruction, and
329 does not pass through the instruction fifo more than once.
331 \item The {\tt P} bits are a {\it predicate}; this
332 holds a code which indicates if the instruction should be executed or
333 ignored depending on the state of flags in the dock.
337 \subsection{Loop Counters}
339 A programmer can perform two types of loops: {\it inner} loops of only
340 one instruction and {\it outer} loops of multiple instructions. Inner
341 loops may be nested within an outer loop, but no other nesting of
344 The dock has two loop counters, one for each kind of loop:
347 \item {\tt OLC} is the Outer Loop Counter
348 \item {\tt ILC} is the Inner Loop Counter
351 The {\tt OLC} applies to all instructions and can hold integers {\tt
354 The {\tt ILC} applies only to {\tt move} instructions and can hold
355 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
356 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
357 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
358 executes until interrupted by a torpedo. After every {\tt move}
359 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
360 to {\tt 1}, {\it not to 0}).
363 \subsection{Flags and Predication}
365 The pump has three flags: {\tt A}, {\tt B}, and {\tt C}.
368 \item The {\tt A} and {\tt B} flags are general-purpose flags which
369 may be set and cleared by the programmer.
373 % The {\tt L} flag, known as the {\it last} flag, is set whenever
374 % the value in the outer counter ({\tt OLC}) is one,
377 % that the dock is in the midst of the last iteration of an
378 % outer loop. This flag can be used to perform certain
379 % operations (such as sending a completion token) only on the last
380 % iteration of an outer loop.
382 \item The {\tt C} flag is known as the {\it control} flag, and may be
383 set by the {\tt move} instruction based on information from the
384 ship or from an inbound packet. See the {\tt move} instruction
390 The {\tt P} field specifies a three-bit {\it predicate}. The
391 predicate determines which conditions must be true in order for the
392 instruction to execute; if it is not executed, it is simply {\it
393 ignored}. The table below shows what conditions must be true in
394 order for an instruction to execute:
397 \begin{tabular}{|r|ll|}\hline
398 Code & Execute & if \\\hline
399 {\tt 000:} & {\tt OLC$\neq$0} & and {\tt A=0} \\
400 {\tt 001:} & {\tt OLC$\neq$0} & and {\tt A=1} \\
401 {\tt 010:} & {\tt OLC$\neq$0} & and {\tt B=0} \\
402 {\tt 011:} & {\tt OLC$\neq$0} & and {\tt B=1} \\
403 {\tt 100:} & Unused & \\
404 {\tt 101:} & {\tt OLC=0} & \\
405 {\tt 110:} & {\tt OLC$\neq$0} & \\
406 {\tt 111:} & always & \\
411 \subsection{The Hatch}
413 What follows is a conservative approximation of the actual behavior of
415 For complete details on the behavior of the hatch, see
416 \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50}.
418 For the purposes of this section, instructions will be
419 classified into three categories: one-shot instructions ({\tt OS=1}),
420 requeueable instructions ({\tt OS=0}), and {\tt tail} instructions.
422 To avoid deadlock, the programmer must ensure that:
426 \item A requeueable instruction is never followed immediately by a
429 \item A one-shot instruction is never followed immediately by a {\tt
432 \item No contiguous sequence of requeueable instructions is longer
433 than the length of the instruction fifo.
435 \item If a requeueable instruction is preceded by a one-shot
436 instruction or a {\tt tail}, then it must be the case that {\tt
437 OLC>0} both before and after the first time that instruction
440 \item If {\tt OLC=0}, only a one-shot instruction may set it to a
445 The dock guarantees that:
449 \item If a requeueable instruction is preceded by a one-shot
450 instruction or a {\tt tail}, then the {\it following}
451 instruction will not execute until a {\tt tail} has reached the
454 \item Once a {\tt tail} instruction reaches the hatch, no further
455 instructions will be enqueued until a requeueable instruction
456 reaches the execution stage and {\tt OLC=0}.
464 When an instruction arrives on deck, two concurrent processes are
469 \item If the instruction on deck is a requeueable instruction
470 ({\tt OS=1}) and the outer loop counter is nonzero ({\tt
471 OLC>0}), a copy of the instruction is requeued.
477 If the instruction's predicate condition is not met (see
478 section on predicates), do nothing.
481 {\it Otherwise} if the instruction is interruptible ({\tt I=1})
482 and a torpedo is present in the waiting area: consume the
483 torpedo, set the outer loop counter to zero ({\tt OLC=0}) and
484 set the inner loop counter to one ({\tt ILC=1}).
487 {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it
488 not} a {\tt move}: execute the instruction.
497 \section{Instructions}
499 The dock supports four instructions:
500 {\tt move} (variants: {\tt moveto}, {\tt dispatch}),
507 \subsection{{\tt move}}
509 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
511 \begin{bytefield}{26}
512 \bitheader[b]{14-20}\\
526 \begin{bytefield}{26}
527 \bitheader[b]{0,12,13}\\
528 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
531 \bitbox{13}{\tt Immediate}
534 \begin{bytefield}{26}
535 \bitheader[b]{11,12,13}\\
536 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:25]\to Path}})\ \ }
545 \begin{bytefield}{26}
546 \bitheader[b]{11,12,13}\\
547 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
558 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
559 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
560 \item {\tt Dc} - Data Capture: pulse the data latch.
561 \item {\tt Do} - Data Output: fill the data successor.
562 \item {\tt To} - Token Output: fill the token successor.
565 The data successor and token successor must both be empty in order for
566 a {\tt move} instruction to attempt execution.
568 Every time the {\tt move} instruction executes, the {\tt C} flag may
572 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
573 of the incoming packet if {\tt Di} or {\tt Ti} is set.
575 \item At an {\it output} dock the {\tt C} flag is set to a value
576 provided by the ship if the {\tt Di} bit is set, and to the
577 signal bit of the incoming packet if {\tt Di} is clear and {\tt
585 \subsection{{\tt set}}
587 The {\tt set} command is used to set or decrement the inner loop
588 counter, outer loop counter, and data latch.
590 \newcommand{\bitsSet}{
591 \setlength{\bitwidth}{5mm}
593 \begin{bytefield}{26}
594 \bitheader[b]{19-25}\\
604 \begin{bytefield}{26}
605 \bitheader[b]{0,5,12-18}\\
606 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
608 \bitbox{4}{\tt 1000\color{black}}
611 \bitbox{6}{\tt Immediate}
614 \begin{bytefield}{26}
615 \bitheader[b]{12-18}\\
616 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
618 \bitbox{4}{\tt 1000\color{black}}
623 \begin{bytefield}{26}
624 \bitheader[b]{12-18}\\
625 \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
627 \bitbox{4}{\tt 1000\color{black}}
632 \begin{bytefield}{26}
633 \bitheader[b]{0,5,6,12-18}\\
634 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
636 \bitbox{4}{\tt 0100\color{black}}
640 \bitbox{6}{\tt Immediate}
643 \begin{bytefield}{26}
644 \bitheader[b]{6,12-18}\\
645 \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
647 \bitbox{4}{\tt 0100\color{black}}
654 \begin{bytefield}{26}
655 \bitheader[b]{12-18}\\
656 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
658 \bitbox{4}{\tt 0100\color{black}}
663 \begin{bytefield}{26}
664 \bitheader[b]{0,13-18}\\
665 \bitbox[1]{6}{\raggedleft \footnotesize {\tt 0-Extended Immediate}\to{\tt Data Latch}}
667 \bitbox{4}{\tt 0010\color{black}}
669 \bitbox{14}{\tt Immediate}
672 \begin{bytefield}{26}
673 \bitheader[b]{0,13-18}\\
674 \bitbox[1]{6}{\raggedleft \footnotesize {\tt 1-Extended Immediate}\to{\tt Data Latch}}
676 \bitbox{4}{\tt 0010\color{black}}
678 \bitbox{14}{\tt Immediate}
681 \begin{bytefield}{26}
682 \bitheader[b]{0,5,6,11,15-18}\\
683 \bitbox[1]{6}{\raggedleft {\tt Update Flags}}
685 \bitbox{4}{\tt 0001\color{black}}
687 \bitbox{6}{\tt nextA}
688 \bitbox{6}{\tt nextB}
697 The FleetTwo implementation is likely to have an unarchitected
698 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
699 with the possibly-extended literal {\it at the time that the {\tt set}
700 instruction comes on deck}. This latch is then copied into the data
701 latch when a {\tt set Data Latch} instruction
702 executes\color{black}.
704 Each of the {\tt nextA} and {\tt nextB} fields has the following
705 structure, and indicates which old flag values should be logically
706 {\tt OR}ed together to produce the new flag value:
712 \bitbox{1}{${\text{\tt A}}$}
713 \bitbox{1}{$\overline{\text{\tt A}}$}
714 \bitbox{1}{${\text{\tt B}}$}
715 \bitbox{1}{$\overline{\text{\tt B}}$}
716 \bitbox{1}{${\text{{\tt C}\ }}$}
717 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
721 Each bit corresponds to one possible input; all inputs whose bits are
722 set are {\tt OR}ed together, and the resulting value is assigned to
723 the flag. Note that if none of the bits are set, the value assigned
724 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
725 OR}ing any flag with its complement, and that {\tt set Flags} can
726 be used to create a {\tt nop} (no-op) by setting each flag to itself.
732 \subsection{{\tt shift}}
734 \newcommand{\shiftImmediateSize}{19}
736 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
737 bits. When a {\tt shift} instruction is executed, this immediate is copied
738 into the least significant \shiftImmediateSize\ bits of the data latch,
739 and the remaining most significant bits of the data latch are loaded
740 with the value formerly in the least significant bits of the data latch.
741 In this manner, large literals can be built up by ``shifting'' them
742 into the data latch \shiftImmediateSize\ bits at a time.
744 \newcommand{\bitsShift}{
745 \setlength{\bitwidth}{5mm}
747 \begin{bytefield}{26}
748 \bitheader[b]{0,18-20}\\
755 \bitbox{\shiftImmediateSize}{Immediate}
760 The FleetTwo implementation is likely to have an unarchitected
761 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
762 with the literal {\it at the time that the {\tt shift} instruction
763 comes on deck}. This latch is then copied into the data latch when
764 the instruction executes.
768 \subsection{{\tt tail}}
770 \newcommand{\bitsTail}{
771 \setlength{\bitwidth}{5mm}
773 \begin{bytefield}{26}
774 \bitheader[b]{19-20}\\
785 When a {\tt tail} instruction reaches the hatch and the hatch is open,
786 it seals the hatch. The {\tt tail} instruction does not enter the
791 %\subsection{{\tt takeOuterLoopCounter}}
793 %\setlength{\bitwidth}{5mm}
795 %\begin{bytefield}{26}
796 % \bitheader[b]{16-19,21}\\
810 %This instruction copies the value in the outer loop counter {\tt OLC}
811 %into the least significant bits of the data latch and leaves all other
812 %bits of the data latch unchanged.
814 %\subsection{{\tt takeInnerLoopCounter}}
816 %\setlength{\bitwidth}{5mm}
818 %\begin{bytefield}{26}
819 % \bitheader[b]{16-19,21}\\
833 %This instruction copies the value in the inner loop counter {\tt ILC}
834 %into the least significant bits of the data latch and leaves all other
835 %bits of the data latch unchanged.
840 %%\subsection{{\tt interrupt}}
842 %%\setlength{\bitwidth}{5mm}
844 %\begin{bytefield}{26}
845 % \bitheader[b]{0,5,16-19,21}\\
856 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
857 %there for the {\tt OD} stage to be full with an instruction that has
858 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
859 %{\it will not execute}, but {\it may reloop} if the conditions for
861 %\footnote{The ability to interrupt an instruction yet have it reloop is very
862 %useful for processing chunks of data with a fixed size header and/or
863 %footer and a variable length body.}
866 %\subsection{{\tt massacre}}
868 %\setlength{\bitwidth}{5mm}
870 %\begin{bytefield}{26}
871 % \bitheader[b]{16-19,21}\\
883 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
884 %for the {\tt OD} stage to be full with an instruction that has the
885 %{\tt IM} bit set. When this occurs, all instructions in the
886 %instruction fifo (including {\tt OD}) are retired.
888 %\subsection{{\tt clog}}
890 %\setlength{\bitwidth}{5mm}
892 %\begin{bytefield}{26}
893 % \bitheader[b]{16-19,21}\\
905 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
906 %no more instructions will be executed until an {\tt unclog} is
909 %\subsection{{\tt unclog}}
911 %\setlength{\bitwidth}{5mm}
913 %\begin{bytefield}{26}
914 % \bitheader[b]{16-19,21}\\
920 % \bitbox[lrtb]{2}{11}
926 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
927 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
928 %instructions retire.
930 %Note that issuing an {\tt unclog} instruction to a dock which is not
931 %clogged and whose instruction fifo contains no {\tt clog} instructions
932 %will cause the dock to deadlock.
937 \section*{Instruction Encoding Map\color{black}}
939 \hspace{-1cm}{\tt shift}\\
942 \hspace{-1cm}{\tt set}\\
945 \hspace{-1cm}{\tt move}\\
948 \hspace{-1cm}{\tt tail}\\
955 \epsfig{file=all,height=5in,angle=90}
958 \subsection*{Input Dock}
959 \epsfig{file=in,width=8in,angle=90}
962 \subsection*{Output Dock}
963 \epsfig{file=out,width=8in,angle=90}
967 %\epsfig{file=ports,height=5in,angle=90}
970 %\epsfig{file=best,height=5in,angle=90}