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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
74 & Factored in Russell Kao's comments (thanks!)\\
75 & Added mechanism for setting C-flag from fabric even on outboxes\\
77 & Made {\tt OLC} test a predicate-controlled condition\\
78 & Rewrote ``on deck'' section \\
79 & Added ``{\tt unset}'' value for {\tt ILC}\\
80 & Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
83 & added comment about address-to-path ship \\
84 & changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
85 & changed the order of instructions in the encoding map \\
87 & added epilogue fifo to diagrams \\
88 & indicated that a token sent to the instruction port is treated as a torpedo \\
90 & replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
91 & replaced {\tt literal} with {\tt shift} instruction \\
93 & Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
94 & Removed ability to manually set the {\tt C} flag \\
95 & Expanded predicate field to three bits \\
96 & New literals scheme (via shifting) \\
97 & Instruction encoding changes made at Ivan's request (for layout purposes) \\
98 & Added summary of instruction encodings on last page \\
100 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
102 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
103 %& update table 3.1.2 \\
104 %& rename {\tt S} flag to {\tt C} \\
105 %& noted that {\tt setFlags} can be used as {\tt nop} \\
107 %& removed the {\tt L} flag (epilogues can now do this) \\
108 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
109 %& renamed {\tt data} instruction to {\tt literal} \\
110 %& renamed {\tt send} instruction to {\tt move} \\
112 %& added ``if its predicate is true'' to repeat count \\
113 %& added note that red wires do not contact ships \\
114 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
115 %& removed black dot from diagrams \\
116 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
117 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
118 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
119 %& added section ``Torpedo Details'' \\
120 %& removed {\tt torpedo} instruction \\
123 %& renamed loop+repeat to outer+inner (not in red) \\
124 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
125 %& rewrote ``inner and outer loops'' section \\
126 %& updated all diagrams \\
129 %& Moved address bits to the LSB-side of a 37-bit instruction \\
130 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
131 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
132 %& Created the {\tt Hold} field \\
133 %& Changed how ReLooping works \\
134 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
141 \epsfig{file=all,height=1.5in}
142 \epsfig{file=overview-new,height=1.5in}
147 \section{Overview of Fleet}
149 A Fleet processor is organized around a {\it switch fabric}, which is
150 a packet-switched network with reliable in-order delivery. The switch
151 fabric is used to carry data between different functional units,
152 called {\it ships}. Each ship is connected to the switch fabric by
153 one or more programmable elements known as {\it docks}.
155 A {\it path} specifies a route through the switch fabric from a
156 particular {\it source} to a particular {\it destination}. The
157 combination of a path and a single word to be delivered is called a
158 {\it packet}. The switch fabric carries packets from their sources to
159 their destinations. Each dock has two destinations: one for {\it
160 instructions} and one for {\it data}. A Fleet is programmed by
161 depositing instruction packets into the switch fabric with paths that
162 will lead them to instruction destinations of the docks at which they
165 When a packet arrives at the instruction destination of a dock, it is
166 enqueued for execution. Before the instruction executes, it may cause
167 the dock to wait for a packet to arrive at the dock's data destination
168 or for a value to be presented by the ship. When an instruction
169 executes it may consume this data and may present a data value to the
170 ship or transmit a packet.
172 When an instruction sends a packet into the switch fabric, it may
173 specify that the payload of the packet is irrelevant. Such packets
174 are known as {\it tokens}, and consume less energy than data packets.
178 \epsfig{file=overview-new,width=2.5in}\\
179 {\it Overview of a Fleet processor; gray shading represents the switch
180 fabric; docks are shown in blue.}
186 \section{The FleetTwo Dock}
188 The diagram below represents a conceptual view of the interface
189 between ships and the switch fabric; actual implementation circuitry
193 \epsfig{file=all,width=3.5in}\\
194 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
195 blue lines carry either tokens or data words, red lines carry either
196 instructions or torpedoes, and dashed lines carry only tokens.}
199 Each dock consists of a {\it data latch}, which is as wide as a single
200 machine word and a {\it pump}, which is a circular fifo of
201 instruction-width latches. The values in the pump control the data
202 latch. The dock also includes a {\it path latch}, which
203 stores the path along which outgoing packets will be sent.\color{black}
205 Note that the pump in each dock has a destination of its own; this is
206 the {\it instruction destination} mentioned in the previous section.
208 From any source to any dock's data destination there are
209 two distinct paths which differ by a single bit. This bit is known as
210 the ``signal'' bit, and the routing of a packet is not affected by it;
211 the signal bit is used to pass control values between docks. Note that paths
212 terminating at an {\it instruction} destination need not have a signal
216 \section{Instructions}
218 In order to cause an instruction to execute, the programmer must first
219 arrange for that instruction word to arrive in the data latch of some
220 output dock. For example, this might be the ``data read'' output dock
221 of the memory access ship or the output of a fifo ship. Once an
222 instruction has arrived at this output dock, it is {\it dispatched} by
223 sending it to the {\it instruction port} of the dock at which it is to
226 Each instruction is 26 bits long, which makes it possible for an
227 instruction and an 11-bit path to fit in a single word of memory.
228 This path is the path from the {\it dispatching} dock to the {\it
231 \setlength{\bitwidth}{3.5mm}
233 \begin{bytefield}{37}
234 \bitheader[b]{0,10,11,36}\\
235 \bitbox{26}{instruction}
236 \bitbox{11}{dispatch path}
242 \subsection{Life Cycle of an Instruction}
244 The diagram below shows an input dock for purposes of illustration:
247 \epsfig{file=in,width=4in}\\
251 Note the mux on the path between {\tt EF} (epilogue fifo) and {\tt IF}
252 (instruction fifo); this is known as ``the hatch''. The hatch has two
253 states: sealed and unsealed. When the machine powers up, the hatch is
254 unsealed; it is sealed by the {\tt tail} instruction and unsealed
255 whenever the outer loop counter is set to zero (for any
256 reason\footnote{this includes {\tt OLC} being decremented to zero, a
257 {\tt set} instruction, or the occurrence
260 When an instruction arrives at the epilogue fifo ({\tt EF}), it waits
261 there until the hatch is in the unsealed state; the instruction then
262 enters the instruction fifo. When an instruction emerges from the
263 instruction fifo, it arrives at the ``on deck'' ({\tt OD}) stage,
264 where it may execute.
267 \epsfig{file=out,width=4in}\\
271 \subsubsection{Torpedoes}
273 A token sent to an instruction destination is called a {\it torpedo}.
274 When a torpedo arrives at the tail of {\tt EF}, it is deposited in a
275 waiting area (not shown) rather than being enqueued into {\tt EF}.
277 There is a latch (not shown) called the {\it torpedo acknowledgment path
278 latch} ({\tt TAPL}) which stores a path. When a torpedo is consumed
279 (see section ``On Deck''), a token is sent along the path held in this
282 \subsection{Format of an Instruction}
284 All instruction words have the following format:
286 \newcommand{\bitsHeader}{
292 \setlength{\bitwidth}{3.5mm}
294 \begin{bytefield}{37}
295 \bitheader[b]{0,10,11,31,32,34-36}\\
300 \bitbox{11}{dispatch path}
305 \item The {\tt I} bit stands for {\tt Interruptible}, and indicates if an
306 instruction is vulnerable to torpedoes.
308 \item The {\tt OS} (``One Shot'') bit indicates whether or not this
309 instruction can pass through the pump more than once. If set to
310 {\tt 1}, then the instruction is a ``one-shot'' instruction, and
311 does not pass through the instruction fifo more than once.
313 \item The {\tt P} bits are a {\it predicate}; this
314 holds a code which indicates if the instruction should be executed or
315 ignored depending on the state of flags in the dock.
319 \subsection{Loop Counters}
321 A programmer can perform two types of loops: {\it inner} loops of only
322 one instruction and {\it outer} loops of multiple instructions. Inner
323 loops may be nested within an outer loop, but no other nesting of
326 The dock has two loop counters, one for each kind of loop:
329 \item {\tt OLC} is the Outer Loop Counter
330 \item {\tt ILC} is the Inner Loop Counter
333 The {\tt OLC} applies to all instructions and can hold integers {\tt
336 The {\tt ILC} applies only to {\tt move} instructions and can hold
337 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
338 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
339 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
340 executes until interrupted by a torpedo. After every {\tt move}
341 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
342 to {\tt 1}, {\it not to 0}).
345 \subsection{Flags and Predication}
347 The pump has three flags: {\tt A}, {\tt B}, and {\tt C}.
350 \item The {\tt A} and {\tt B} flags are general-purpose flags which
351 may be set and cleared by the programmer.
355 % The {\tt L} flag, known as the {\it last} flag, is set whenever
356 % the value in the outer counter ({\tt OLC}) is one,
359 % that the dock is in the midst of the last iteration of an
360 % outer loop. This flag can be used to perform certain
361 % operations (such as sending a completion token) only on the last
362 % iteration of an outer loop.
364 \item The {\tt C} flag is known as the {\it control} flag, and may be
365 set by the {\tt move} instruction based on information from the
366 ship or from an inbound packet. See the {\tt move} instruction
372 The {\tt P} field specifies a three-bit {\it predicate}. The
373 predicate determines which conditions must be true in order for the
374 instruction to execute; if it is not executed, it is simply {\it
375 ignored}. The table below shows what conditions must be true in
376 order for an instruction to execute:
379 \begin{tabular}{|r|ll|}\hline
380 Code & Execute & if \\\hline
381 {\tt 000:} & {\tt OLC$\neq$0} & and {\tt A=0} \\
382 {\tt 001:} & {\tt OLC$\neq$0} & and {\tt A=1} \\
383 {\tt 010:} & {\tt OLC$\neq$0} & and {\tt B=0} \\
384 {\tt 011:} & {\tt OLC$\neq$0} & and {\tt B=1} \\
385 {\tt 100:} & {\tt OLC$\neq$0} & and {\tt C=0} \\
386 {\tt 101:} & {\tt OLC$\neq$0} & and {\tt C=1} \\
387 {\tt 110:} & {\tt OLC$\neq$0} & \\
388 {\tt 111:} & always & \\
395 When an instruction arrives on deck, two concurrent processes are
396 started. No subsequent instruction may come on deck until both
397 processes have completed:
403 \item If the outer loop counter is zero ({\tt OLC=0}) or the
404 instruction on deck is a one-shot instruction ({\tt
406 \item {\it Otherwise} wait for the hatch to be sealed and
407 enqueue a copy of the instruction currently on deck.
414 If the instruction's predicate condition is not met (see
415 section on predicates), do nothing.
418 {\it Otherwise} if the instruction is interruptible ({\tt I=0})
419 and a torpedo is present in the waiting area: consume the
420 torpedo, set the outer loop counter to zero ({\tt OLC=0}),
421 unseal the hatch, and transmit a token along in the
422 {\it torpedo acknowledgment path latch} ({\tt TAPL}).
425 {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it
426 not} a {\tt move}: execute the instruction.
435 \section{Instructions}
437 The dock supports for instructions:
438 {\tt move} (variants: {\tt moveto}, {\tt dispatch}),
445 \subsection{{\tt move} (variants: {\tt moveto}, {\tt dispatch})}
447 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
449 \begin{bytefield}{26}
450 \bitheader[b]{14-20}\\
464 \begin{bytefield}{26}
465 \bitheader[b]{0,12,13}\\
466 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Payload\to Path})}
469 \bitbox{13}{\tt Payload}
472 \begin{bytefield}{26}
473 \bitheader[b]{11,12,13}\\
474 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:25]\to Path}})\ \ }
483 \begin{bytefield}{26}
484 \bitheader[b]{11,12,13}\\
485 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
496 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
497 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
498 \item {\tt Dc} - Data Capture: pulse the data latch.
499 \item {\tt Do} - Data Output: fill the data successor.
500 \item {\tt To} - Token Output: fill the token successor.
503 The data successor and token successor must both be empty in order for
504 a {\tt move} instruction to attempt execution.
506 Every time the {\tt move} instruction executes, the {\tt C} flag may
510 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
511 of the incoming packet if {\tt Di} or {\tt Ti} is set.
513 \item At an {\it output} dock the {\tt C} flag is set to a value
514 provided by the ship if the {\tt Di} bit is set, and to the
515 signal bit of the incoming packet if {\tt Di} is clear and {\tt
523 \subsection{{\tt set}}
525 The {\tt set} command is used to set or decrement the inner loop
526 counter, outer loop counter, and data latch.
528 \newcommand{\bitsSet}{
529 \setlength{\bitwidth}{5mm}
531 \begin{bytefield}{26}
532 \bitheader[b]{0,13-15,16-20}\\
547 \begin{tabular}{|r|r|l|l|}\hline
548 Source & SRC & DST & Destination \\\hline
550 Payload & 00 & 000 & OLC \\
551 Data Latch & 01 & 000 & OLC \\
552 OLC-1 & 10 & 000 & OLC \\
553 Payload & 00 & 001 & ILC \\
554 Data Latch & 01 & 001 & ILC \\
555 $\infty$ & 10 & 001 & ILC \\
556 Payload & 00 & 010 & TAPL \\
557 Payload, 0-extend & 01 & 100 & Data Latch \\
558 Payload, 1-extend & 10 & 100 & Data Latch \\
559 see below & & 111 & Flags \\
564 The FleetTwo implementation is likely to have an unarchitected
565 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
566 with the possibly-extended literal {\it at the time that the {\tt set}
567 instruction comes on deck}. This latch is then copied into the data
568 latch when a {\tt set Data Latch} instruction
569 executes\color{black}.
571 If the {\tt Dest} field is {\tt flags}, the {\tt Payload} field is
572 interpreted as two fields, each giving the truth table for the new
573 value of one of the two user-settable flags:
576 \setlength{\bitwidth}{5mm}
578 \begin{bytefield}{26}
579 \bitheader[b]{0,5,6,11}\\
596 Each field has the following structure, and indicates which old flag
597 values should be logically {\tt OR}ed together to produce the new flag
604 \bitbox{1}{${\text{\tt A}}$}
605 \bitbox{1}{$\overline{\text{\tt A}}$}
606 \bitbox{1}{${\text{\tt B}}$}
607 \bitbox{1}{$\overline{\text{\tt B}}$}
608 \bitbox{1}{${\text{{\tt C}\ }}$}
609 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
613 Each bit corresponds to one possible input; all inputs whose bits are
614 set are {\tt OR}ed together, and the resulting value is assigned to
615 the flag. Note that if none of the bits are set, the value assigned
616 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
617 OR}ing any flag with its complement, and that {\tt set Flags} can
618 be used to create a {\tt nop} (no-op) by setting each flag to itself.
624 \subsection{{\tt shift}}
626 \newcommand{\shiftPayloadSize}{19}
628 Each {\tt shift} instruction carries a payload of \shiftPayloadSize\
629 bits. When a {\tt shift} instruction is executed, this payload is copied
630 into the least significant \shiftPayloadSize\ bits of the data latch,
631 and the remaining most significant bits of the data latch are loaded
632 with the value formerly in the least significant bits of the data latch.
633 In this manner, large literals can be built up by ``shifting'' them
634 into the data latch \shiftPayloadSize\ bits at a time.
636 \newcommand{\bitsShift}{
637 \setlength{\bitwidth}{5mm}
639 \begin{bytefield}{26}
640 \bitheader[b]{0,18-20}\\
647 \bitbox{\shiftPayloadSize}{Payload}
652 The FleetTwo implementation is likely to have an unarchitected
653 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
654 with the literal {\it at the time that the {\tt shift} instruction
655 comes on deck}. This latch is then copied into the data latch when
656 the instruction executes.
660 \subsection{{\tt tail}}
662 \newcommand{\bitsTail}{
663 \setlength{\bitwidth}{5mm}
665 \begin{bytefield}{26}
666 \bitheader[b]{19-20}\\
677 When a {\tt tail} instruction reaches the hatch, it seals the hatch.
678 The {\tt tail} instruction does not enter the instruction fifo.
682 %\subsection{{\tt takeOuterLoopCounter}}
684 %\setlength{\bitwidth}{5mm}
686 %\begin{bytefield}{26}
687 % \bitheader[b]{16-19,21}\\
701 %This instruction copies the value in the outer loop counter {\tt OLC}
702 %into the least significant bits of the data latch and leaves all other
703 %bits of the data latch unchanged.
705 %\subsection{{\tt takeInnerLoopCounter}}
707 %\setlength{\bitwidth}{5mm}
709 %\begin{bytefield}{26}
710 % \bitheader[b]{16-19,21}\\
724 %This instruction copies the value in the inner loop counter {\tt ILC}
725 %into the least significant bits of the data latch and leaves all other
726 %bits of the data latch unchanged.
731 %%\subsection{{\tt interrupt}}
733 %%\setlength{\bitwidth}{5mm}
735 %\begin{bytefield}{26}
736 % \bitheader[b]{0,5,16-19,21}\\
747 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
748 %there for the {\tt OD} stage to be full with an instruction that has
749 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
750 %{\it will not execute}, but {\it may reloop} if the conditions for
752 %\footnote{The ability to interrupt an instruction yet have it reloop is very
753 %useful for processing chunks of data with a fixed size header and/or
754 %footer and a variable length body.}
757 %\subsection{{\tt massacre}}
759 %\setlength{\bitwidth}{5mm}
761 %\begin{bytefield}{26}
762 % \bitheader[b]{16-19,21}\\
774 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
775 %for the {\tt OD} stage to be full with an instruction that has the
776 %{\tt IM} bit set. When this occurs, all instructions in the
777 %instruction fifo (including {\tt OD}) are retired.
779 %\subsection{{\tt clog}}
781 %\setlength{\bitwidth}{5mm}
783 %\begin{bytefield}{26}
784 % \bitheader[b]{16-19,21}\\
796 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
797 %no more instructions will be executed until an {\tt unclog} is
800 %\subsection{{\tt unclog}}
802 %\setlength{\bitwidth}{5mm}
804 %\begin{bytefield}{26}
805 % \bitheader[b]{16-19,21}\\
811 % \bitbox[lrtb]{2}{11}
817 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
818 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
819 %instructions retire.
821 %Note that issuing an {\tt unclog} instruction to a dock which is not
822 %clogged and whose instruction fifo contains no {\tt clog} instructions
823 %will cause the dock to deadlock.
828 \section*{Instruction Encoding Map\color{black}}
830 \hspace{-1cm}{\tt shift}\\
833 \hspace{-1cm}{\tt set}\\
836 \hspace{-1cm}{\tt move}\\
839 \hspace{-1cm}{\tt tail}\\
846 \epsfig{file=all,height=5in,angle=90}
849 \subsection*{Input Dock}
850 \epsfig{file=in,width=8in,angle=90}
853 \subsection*{Output Dock}
854 \epsfig{file=out,width=8in,angle=90}
858 %\epsfig{file=ports,height=5in,angle=90}
861 %\epsfig{file=best,height=5in,angle=90}