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55 \title{\vspace{-1cm}The FleetTwo Dock}
67 & Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
68 & Removed ability to manually set the {\tt C} flag \\
69 & Expanded predicate field to three bits \\
70 & New literals scheme (via shifting) \\
71 & Instruction encoding changes made at Ivan's request (for layout purposes) \\
72 & Added summary of instruction encodings on last page \\
75 & removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
77 & extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
78 & update table 3.1.2 \\
79 & rename {\tt S} flag to {\tt C} \\
80 & noted that {\tt setFlags} can be used as {\tt nop} \\
82 & removed the {\tt L} flag (epilogues can now do this) \\
83 & removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
84 & renamed {\tt data} instruction to {\tt literal} \\
85 & renamed {\tt send} instruction to {\tt move} \\
87 %& added ``if its predicate is true'' to repeat count \\
88 %& added note that red wires do not contact ships \\
89 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
90 %& removed black dot from diagrams \\
91 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
92 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
93 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
94 %& added section ``Torpedo Details'' \\
95 %& removed {\tt torpedo} instruction \\
98 %& renamed loop+repeat to outer+inner (not in red) \\
99 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
100 %& rewrote ``inner and outer loops'' section \\
101 %& updated all diagrams \\
104 %& Moved address bits to the LSB-side of a 37-bit instruction \\
105 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
106 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
107 %& Created the {\tt Hold} field \\
108 %& Changed how ReLooping works \\
109 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
116 \epsfig{file=overview,width=1.5in}
117 \epsfig{file=indock,width=3in}
122 \section{Overview of Fleet}
124 A Fleet processor consists of a {\it switch fabric} with several
125 functional units called {\it ships} connected to it. At each
126 connection between a ship and the switch fabric lies a programmable
127 element known as the {\it dock}.
129 A {\it path} specifies a route through the switch fabric from a
130 particular {\it source} to a particular {\it destination}. The
131 combination of a path and a single word {\it payload} is called a {\it packet}. The
132 switch fabric carries packets from their sources to their
133 destinations. Each dock has two destinations: one for {\it
134 instructions} and one for {\it data}. A Fleet is programmed by
135 depositing packets into the switch fabric; these packets' paths lead
136 them to the instruction destinations of the docks.
138 When a packet arrives at the instruction destination of a dock, it is
139 enqueued for execution. Before the instruction executes, it may cause
140 the dock to wait for a packet to arrive at the dock's data destination
141 or for a value to be presented by the ship. It may present a data
142 value to the ship or transmit it for transmission to some other
145 When an instruction sends a packet into the switch fabric, it may
146 specify that the payload of the packet is irrelevant. Such packets
147 are known as {\it tokens}, and consume less energy than data packets.
148 From a programmer's perspective, a token packet is indistinguishable
149 from a data packet with a unknown payload.
151 In the diagram below, the red wires carry instructions and the blue
152 wires carry data; the switch fabric (gray area) carries both. Notice
153 that the red (instruction) wires do not contact the ships. This is an
154 advantage: ships are designed without any consideration for the
155 instructions used to program their docks.
158 \epsfig{file=overview,width=2.5in}\\
159 {\it Overview of a Fleet processor; gray shading represents a
160 packet-switched network fabric; blue lines carry data, red lines
167 \section{The FleetTwo Pump}
169 The diagram below represents a {\it programmer's} conceptual view of
170 the interface between ships and the switch fabric. Actual
171 implementation circuitry may differ substantially. Sources and
172 destinations that can send and receive only tokens -- not data items
173 -- are drawn as dashed lines.
176 \epsfig{file=indock,width=3.5in}\\
177 {\it an ``input'' dock}
179 \epsfig{file=outdock,width=3.5in}\\
180 {\it an ``output'' dock}
183 The term {\it port} refers to an interface to the ship, the {\it
184 dock} connecting it to the switch fabric, and the corresponding
185 sources and destinations on the switch fabric.
187 Each dock consists of a {\it data latch}, which is as wide as a single
188 machine word and a {\it pump}, which is a circular fifo of
189 instruction-width latches. The values in the pump control the data
192 Note that the pump in each dock has a destination of its own; this is
193 the {\it instruction destination} mentioned in the previous section.
194 Note that unlike all other destinations, there is no buffering fifo
195 guarding this one. The size of these fifos are exposed to the
196 software programmer so he can avoid deadlock.
199 \section{Instructions}
201 In order to cause an instruction to execute, the programmer must first
202 cause that instruction word to arrive in the data latch of some output
203 dock. For example, this might be the ``data read'' output dock of the
204 memory access ship or the output of a fifo ship. Once an instruction
205 has arrived at this output dock, it is {\it dispatched} by sending it
206 to the {\it instruction port} of the dock at which it is to execute.
208 Each instruction is 26 bits long, which makes it possible for an
209 instruction and an 11-bit path to fit in a single word of memory.
210 This path is the path from the {\it dispatching} dock to the {\it
213 \setlength{\bitwidth}{3.5mm}
215 \begin{bytefield}{37}
216 \bitheader[b]{0,10,11,36}\\
217 \bitbox{26}{instruction}
218 \bitbox{11}{dispatch path}
221 {\bf Note:} the instruction encodings below are simply ``something to
222 shoot at'' and a sanity check to make sure we haven't overrun our bit
223 budget. The final instruction encodings will probably be
226 All instruction words have the following format:
228 \newcommand{\bitsHeader}{
234 \setlength{\bitwidth}{3.5mm}
236 \begin{bytefield}{37}
237 \bitheader[b]{0,10,11,36}\\
242 \bitbox{11}{dispatch path}
246 Each instruction word is called a {\it micro instruction}.
247 Collections of one or more micro instruction are known as {\it
248 composite instructions}.
250 The {\tt I} bit stands for {\tt Interruptible}. The {\tt OS} (``One
251 Shot'') bit indicates whether or not this instruction is part of an
252 outer loop. Both of the preceding bits are explained in the next
257 The abbreviation {\tt P} stands for {\it predicate}; this is a two-bit
258 code that indicates if the instruction should be executed or ignored.
263 \subsection{Life Cycle of an Instruction}
265 The diagram below shows an input dock for purposes of illustration
266 (behavior at an output dock is identical).
269 \epsfig{file=indock,width=3in}\\
273 Note the circle on the path between ``instr horn'' and ``instr fifo'';
274 this is known as ``the hatch''. The hatch has two states: sealed and
275 unsealed. When the machine powers up, the hatch is unsealed; it is
276 sealed by the {\tt tail} instruction and unsealed whenever the outer
277 loop counter is set to zero (for any reason\footnote{this
278 includes {\tt OLC} being decremented to zero, a {\tt setOuter} with
279 a literal field of zero, a {\tt setOuter} which copies a zero from
280 the data register to {\tt OLC}, or the occurrence of a
283 When an instruction arrives at the instruction horn, it waits there
284 until the hatch is in the unsealed state. The instruction then enters
285 the instruction fifo. When an instruction emerges from the
286 instruction fifo, it arrives at the ``on deck'' stage, where it may
289 \subsubsection{Inner and Outer Loops}
291 A programmer can perform two types of loops: {\it inner} loops of only
292 one micro-instruction and {\it outer} loops of multiple
293 micro-instructions. Inner loops may be nested within an outer loop,
294 but no other nesting of loops is allowed. The paths used by inner
295 loops and outer loops are shown below:
298 \begin{minipage}{2in}
300 \epsfig{file=inner-loop,width=2in}\\
301 {\it inner loop (in red)}
304 \begin{minipage}{2in}
306 \epsfig{file=outer-loop,width=2in}\\
307 {\it outer loop (in red)}
312 Each type of loop has a counter associated with it: the {\tt ILC}
313 counter for inner loops and the {\tt OLC} counter for outer loops.
314 The inner loop counter applies only to certain ``inner-looping''
315 instructions (see the table below for details). When such an
316 instruction reaches On Deck, if its predicate is true it will execute
317 a number of times equal to {\tt ILC+1}, and leave {\tt ILC=0} after
318 executing. Non-inner-looping instructions and instructions whose
319 predicate is false do not decrement {\tt ILC}.
321 The outer loop counter applies to all instructions {\it except} the
322 instruction {\tt setOuter} with {\tt OS=1}, because such instructions
323 are needed to reset the outer loop counter after it becomes zero.
324 However, predicated {\tt setOuter} with {\tt OS=0} is useful for
325 resetting the loop counter in the middle of the execution of a loop.
327 \subsubsection{On Deck}
329 The table below lists the actions which may be taken when an
330 instruction arrives on deck:
333 \def\side#1{\begin{sideways}\parbox{15mm}{#1}\end{sideways}}
334 \begin{tabular}{|r|ccccc|cccccc|}\hline
335 %&\multicolumn{10}{c}{Predicate}&\\
336 %&\multicolumn{10}{c}{True}&\\\hline
337 &\multicolumn{5}{c}{Outer-Looping} &\multicolumn{5}{c}{One-Shot}&\\
338 &\multicolumn{5}{c}{{\tt (OS=0)}} &\multicolumn{5}{c}{{\tt (OS=1)}}&\\
340 &\side{{\tt literal}}
341 &\side{{\tt setFlags}}
342 &\side{{\tt setInner}}
343 &\side{{\tt setOuter}}
345 &\side{{\tt literal}}
346 &\side{{\tt setFlags}}
347 &\side{{\tt setInner}}
348 &\side{{\tt setOuter}}
351 Wait for hatch sealed, & + & + & + & + & + & - & - & - & - & - & \\
352 then IF0 w/ copy of self & & & & & & & & & & & \\\hline
353 Potentially torpedoable & P+I & P+I & P+I & P+I & P+I & P\color{red}+\color{black}I & P\color{red}+\color{black}I & P\color{red}+\color{black}I & P\color{red}+\color{black}I & PI & \\
354 Execute & P+ & P+ & P+ & P+ & P+ & P\color{red}+\color{black} & P\color{red}+\color{black} & P\color{red}+\color{black} & P\color{red}+\color{black} & P & \\
355 Inner-looping & P+ & - & - & - & - & P & - & - & - & - & \\
359 \begin{tabular}{|r|l|}\hline
360 + & Only if {\tt OLC>0} (ie {\tt OLC} is positive) \\
361 P & Only if predicate is true \\
362 P+ & Only if predicate is true and {\tt OLC>0} \\
363 PI & Only if predicate is true and {\tt I=1}. \\
364 P+I & Only if predicate is true and {\tt OLC>0} and {\tt I=1}. \\\hline
368 {\bf Note:} a non-one-shot instruction may {\it execute} before the
369 hatch is sealed, but may not {\it fill IF0} before the hatch is
370 sealed. The instruction will not vacate On Deck until both of these
371 tasks are complete, so the second non-one-shot instruction in a loop
372 will not execute until the hatch is sealed, {\it but the first
377 \subsubsection{Torpedo}
379 There is a small fifo (not shown) before the latch marked
380 ``Instruction Horn''; after the {\tt tail} instruction seals the
381 hatch, any subsequent instructions will queue up in this fifo until
382 the hatch is unsealed. This is typically used as storage for a ``loop
383 epilogue'' -- a sequence of instructions to be executed after a
384 torpedo arrives or the outer loop counter expires.
386 Each dock has a fourth connection to the switch fabric (not shown),
387 called its {\it torpedo destination}. Anything (even a token) sent to
388 this destination is treated as a torpedo. Note that because this is a
389 distinct destination, instructions or data queued up in the other
390 destination fifos will not prevent a torpedo from occurring.
393 The dock also has a {\it torpedo acknowledgment path latch},
394 which stores the path along which a token should be sent when a
395 torpedo strikes. How this latch is set is yet to be determined.
398 When a data item or token arrives at the torpedo destination, it lies
399 there in wait until On Deck holds a potentially torpedoable
400 instruction (see previous table). Once this is the case, the torpedo
401 causes the inner and outer loop counters to be set to zero (and
402 therefore also unseals the hatch)\footnote{it is unspecified whether
403 the torpedoed instruction is requeued or not; this may or may not
404 occur, nondeterministically. It is the programmer's responsibility
405 to ensure that the program behaves the same whether this happens or
406 not. We think that this will not matter in most situations.} \color{red}and
407 sends a token along the path stored in the torpedo acknowledgment path
414 The pump has three flags: {\tt A}, {\tt B}, and {\tt C}.
417 \item The {\tt A} and {\tt B} flags are general-purpose flags which
418 may be set and cleared by the programmer.
422 % The {\tt L} flag, known as the {\it last} flag, is set whenever
423 % the value in the outer counter ({\tt OLC}) is one,
426 % that the dock is in the midst of the last iteration of an
427 % outer loop. This flag can be used to perform certain
428 % operations (such as sending a completion token) only on the last
429 % iteration of an outer loop.
431 \item The {\tt C} flag is known as the {\it control} flag, and it is
432 set every time the data latch takes on a new value. At outboxes
433 its value is determined by the ship; at inboxes its value is
434 copied from an unused address bit in the destination to which
435 the received value was sent.
438 Many instruction fields are specified as
439 \color{red}three-bit\color{black}\ {\it predicates}. These fields
440 contain one of eight values, indicating if an action should be taken
441 unconditionally or conditionally on one of the {\tt A}, {\tt B}, or
447 \item {\tt 000:} if {\tt A} is set
448 \item {\tt 001:} if {\tt A} is cleared
449 \item {\tt 010:} if {\tt B} is set
450 \item {\tt 011:} if {\tt B} is cleared
453 \item {\tt 100:} if {\tt C} is set
454 \item {\tt 101:} if {\tt C} is cleared
455 \item {\tt 110:} unused
456 \item {\tt 111:} always
463 \section{Instructions}
465 Here is a list of the instructions supported by the dock:
468 \begin{tabular}{|l|}\hline
469 {\tt move} (variants: {\tt moveto}, {\tt dispatch}) \\
482 \subsection{{\tt move} (variants: {\tt moveto}, {\tt dispatch})}
484 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
486 \begin{bytefield}{26}
487 \bitheader[b]{14-19,21}\\
500 %\begin{bytefield}{26}
501 % \bitheader[b]{12-18}\\
502 % \bitbox[]{8}{\raggedleft Input Dock:}
509 %\begin{bytefield}{26}
510 % \bitheader[b]{12-18}\\
511 % \bitbox[]{8}{\raggedleft Output Dock:}
518 \begin{bytefield}{26}
519 \bitheader[b]{0,12,13}\\
520 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt LiteralPath\to Path})}
523 \bitbox{13}{\tt LiteralPath}
526 \begin{bytefield}{26}
527 \bitheader[b]{12,13}\\
528 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\tt DP[37:25]\to Path})\ \ }
537 \begin{bytefield}{26}
538 \bitheader[b]{12,13}\\
539 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
550 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
551 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
552 \item {\tt Dc} - Data Capture: pulse the data latch.
553 \item {\tt Do} - Data Output: fill the data successor.
554 \item {\tt To} - Token Output: fill the token successor.
557 The data successor and token successor must both be empty in order for
558 a {\tt move} instruction to attempt execution.
560 The inner loop counter can hold a number {\tt 0..MAX} or a special
561 value $\infty$. If {\tt ILC} is nonzero after execution of a {\tt
562 move} instruction, the instruction will execute again, and {\tt ILC}
563 will be latched with {\tt (ILC==$\infty$?$\infty$:max(ILC-1, 0))}. When
564 the inner loop counter reaches zero, the instruction ceases executing.
568 \subsection{{\tt literal}}
572 \newcommand{\literalPayloadSize}{17}
574 Each literal instruction carries a payload of \literalPayloadSize\
575 bits. When a literal instruction is executed, this payload is copied
576 into the least significant \literalPayloadSize\ bits of the data latch,
577 and the remaining most significant bits of the data latch are loaded
583 \item The value formerly in the least significant bits of the data latch
586 In this manner, large literals can be built up by ``shifting'' them
587 into the data latch \literalPayloadSize\ bits at a time.
589 \newcommand{\bitsLiteral}{
590 \setlength{\bitwidth}{5mm}
592 \begin{bytefield}{26}
593 \bitheader[b]{0,16-21}\\
600 \bitbox{\literalPayloadSize}{Payload}
606 \begin{tabular}{|r|c|c|c|}\hline
607 sel & D[37:18] & D[17:1] \\\hline
608 00 & D[20:1] & Payload[17:1] \\
609 01 & all 0 & Payload[17:1] \\
610 10 & all 1 & Payload[17:1] \\
611 11 & not used & not used \\
619 \subsection{{\tt setFlags}}
621 \newcommand{\bitsFlags}{\setlength{\bitwidth}{5mm}
623 \begin{bytefield}{26}
624 \bitheader[b]{0,5,6,11,12,16-20}\\
636 When this instruction executes, the flags are updated according to the
637 {\tt nextA} and {\tt nextB} fields; each specifies the new value as
638 the logical {\tt OR} of zero or more inputs:
644 \bitbox{1}{${\text{\tt A}}$}
645 \bitbox{1}{$\overline{\text{\tt A}}$}
646 \bitbox{1}{${\text{\tt B}}$}
647 \bitbox{1}{$\overline{\text{\tt B}}$}
648 \bitbox{1}{${\text{{\tt C}\ }}$}
649 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
653 Each bit corresponds to one possible input; all inputs whose bits are
654 set are {\tt OR}ed together, and the resulting value is assigned to
655 the flag. Note that if none of the bits are set, the value assigned
656 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
657 OR}ing any flag with its complement, and that {\tt setFlags} can
658 be used to create a {\tt nop} (no-op) by setting each flag to itself.
664 \subsection{{\tt setInner}}
666 This instruction loads the inner loop counter with either a literal
667 number, the special value $\infty$, or the contents of the {\tt data}
670 \newcommand{\bitsSetInner}{
671 \setlength{\bitwidth}{5mm}
673 \begin{bytefield}{26}
674 \bitheader[b]{16-19,21}\\
686 \begin{bytefield}{26}
687 \bitbox[r]{18}{\raggedleft from data latch:\hspace{0.2cm}\ }
694 \begin{bytefield}{26}
695 \bitheader[b]{0,5,6,7}\\
696 \bitbox[r]{18}{\raggedleft from literal:\hspace{0.2cm}\ }
698 \bitbox{6}{\tt Literal}
701 \begin{bytefield}{26}
702 \bitheader[b]{0,5,6,7}\\
703 \bitbox[r]{18}{\raggedleft with $\infty$\ \ }
712 \subsection{{\tt setOuter}}
714 This instruction loads the outer loop counter {\tt OLC} with either
715 {\tt max(0,OLC-1)}, a literal or the contents of the {\tt data}
718 \newcommand{\bitsSetOuter}{\setlength{\bitwidth}{5mm}
720 \begin{bytefield}{26}
721 \bitheader[b]{16-19,21,24}\\
733 \begin{bytefield}{26}
734 \bitbox[r]{19}{\raggedleft {\tt max(0,OLC-1)}:\hspace{0.2cm}\ }
742 \begin{bytefield}{26}
743 \bitbox[r]{19}{\raggedleft from data latch:\hspace{0.2cm}\ }
750 \begin{bytefield}{26}
751 \bitheader[b]{0,5,6}\\
752 \bitbox[r]{19}{\raggedleft from literal:\hspace{0.2cm}\ }
754 \bitbox{6}{\tt Literal}
758 %\subsection{{\tt torpedo}}
760 %\setlength{\bitwidth}{5mm}
762 %\begin{bytefield}{26}
763 % \bitheader[b]{0,5,16-19,21}\\
775 %When a {\tt torpedo} instruction reaches the instruction horn, it will
776 %wait there until an instruction is on deck whose {\tt A}rmor bit is
777 %not set. The {\tt torpedo} will then cause ``Process \#2'' of the on
778 %deck instruction to terminate and will set the outer loop counter to zero.
780 \subsection{{\tt tail}}
782 \newcommand{\bitsTail}{
783 \setlength{\bitwidth}{5mm}
785 \begin{bytefield}{26}
786 \bitheader[b]{0,5,16-19,21}\\
797 When a {\tt tail} instruction reaches {\tt IH}, it seals the hatch.
798 The {\tt tail} instruction does not enter the instruction fifo.
802 %\subsection{{\tt takeOuterLoopCounter}}
804 %\setlength{\bitwidth}{5mm}
806 %\begin{bytefield}{26}
807 % \bitheader[b]{16-19,21}\\
821 %This instruction copies the value in the outer loop counter {\tt OLC}
822 %into the least significant bits of the data latch and leaves all other
823 %bits of the data latch unchanged.
825 %\subsection{{\tt takeInnerLoopCounter}}
827 %\setlength{\bitwidth}{5mm}
829 %\begin{bytefield}{26}
830 % \bitheader[b]{16-19,21}\\
844 %This instruction copies the value in the inner loop counter {\tt ILC}
845 %into the least significant bits of the data latch and leaves all other
846 %bits of the data latch unchanged.
851 %%\subsection{{\tt interrupt}}
853 %%\setlength{\bitwidth}{5mm}
855 %\begin{bytefield}{26}
856 % \bitheader[b]{0,5,16-19,21}\\
867 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
868 %there for the {\tt OD} stage to be full with an instruction that has
869 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
870 %{\it will not execute}, but {\it may reloop} if the conditions for
872 %\footnote{The ability to interrupt an instruction yet have it reloop is very
873 %useful for processing chunks of data with a fixed size header and/or
874 %footer and a variable length body.}
877 %\subsection{{\tt massacre}}
879 %\setlength{\bitwidth}{5mm}
881 %\begin{bytefield}{26}
882 % \bitheader[b]{16-19,21}\\
894 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
895 %for the {\tt OD} stage to be full with an instruction that has the
896 %{\tt IM} bit set. When this occurs, all instructions in the
897 %instruction fifo (including {\tt OD}) are retired.
899 %\subsection{{\tt clog}}
901 %\setlength{\bitwidth}{5mm}
903 %\begin{bytefield}{26}
904 % \bitheader[b]{16-19,21}\\
916 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
917 %no more instructions will be executed until an {\tt unclog} is
920 %\subsection{{\tt unclog}}
922 %\setlength{\bitwidth}{5mm}
924 %\begin{bytefield}{26}
925 % \bitheader[b]{16-19,21}\\
931 % \bitbox[lrtb]{2}{11}
937 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
938 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
939 %instructions retire.
941 %Note that issuing an {\tt unclog} instruction to a dock which is not
942 %clogged and whose instruction fifo contains no {\tt clog} instructions
943 %will cause the dock to deadlock.
948 \section*{\color{red}Instruction Encoding Map\color{black}}
966 \epsfig{file=overview,height=5in,angle=90}
969 \subsection*{Input Dock}
970 \epsfig{file=indock,width=7in,angle=90}
973 \subsection*{Output Dock}
974 \epsfig{file=outdock,width=6.5in,angle=90}
978 %\epsfig{file=ports,height=5in,angle=90}
981 %\epsfig{file=best,height=5in,angle=90}