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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
70 & \color{red} When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
71 & \color{red} Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
73 & Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
74 & Reworked encoding of {\tt set} instruction \\
77 & Factored in Russell Kao's comments (thanks!)\\
78 & Added mechanism for setting C-flag from fabric even on outboxes\\
80 & Made {\tt OLC} test a predicate-controlled condition\\
81 & Rewrote ``on deck'' section \\
82 & Added ``{\tt unset}'' value for {\tt ILC}\\
83 & Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
86 & added comment about address-to-path ship \\
87 & changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
88 & changed the order of instructions in the encoding map \\
90 & added epilogue fifo to diagrams \\
91 & indicated that a token sent to the instruction port is treated as a torpedo \\
93 & replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
94 & replaced {\tt literal} with {\tt shift} instruction \\
96 & Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
97 & Removed ability to manually set the {\tt C} flag \\
98 & Expanded predicate field to three bits \\
99 & New literals scheme (via shifting) \\
100 & Instruction encoding changes made at Ivan's request (for layout purposes) \\
101 & Added summary of instruction encodings on last page \\
103 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
105 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
106 %& update table 3.1.2 \\
107 %& rename {\tt S} flag to {\tt C} \\
108 %& noted that {\tt setFlags} can be used as {\tt nop} \\
110 %& removed the {\tt L} flag (epilogues can now do this) \\
111 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
112 %& renamed {\tt data} instruction to {\tt literal} \\
113 %& renamed {\tt send} instruction to {\tt move} \\
115 %& added ``if its predicate is true'' to repeat count \\
116 %& added note that red wires do not contact ships \\
117 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
118 %& removed black dot from diagrams \\
119 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
120 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
121 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
122 %& added section ``Torpedo Details'' \\
123 %& removed {\tt torpedo} instruction \\
126 %& renamed loop+repeat to outer+inner (not in red) \\
127 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
128 %& rewrote ``inner and outer loops'' section \\
129 %& updated all diagrams \\
132 %& Moved address bits to the LSB-side of a 37-bit instruction \\
133 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
134 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
135 %& Created the {\tt Hold} field \\
136 %& Changed how ReLooping works \\
137 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
144 \epsfig{file=all,height=1.5in}
145 \epsfig{file=overview-new,height=1.5in}
150 \section{Overview of Fleet}
152 A Fleet processor is organized around a {\it switch fabric}, which is
153 a packet-switched network with reliable in-order delivery. The switch
154 fabric is used to carry data between different functional units,
155 called {\it ships}. Each ship is connected to the switch fabric by
156 one or more programmable elements known as {\it docks}.
158 A {\it path} specifies a route through the switch fabric from a
159 particular {\it source} to a particular {\it destination}. The
160 combination of a path and a single word to be delivered is called a
161 {\it packet}. The switch fabric carries packets from their sources to
162 their destinations. Each dock has two destinations: one for {\it
163 instructions} and one for {\it data}. A Fleet is programmed by
164 depositing instruction packets into the switch fabric with paths that
165 will lead them to instruction destinations of the docks at which they
168 When a packet arrives at the instruction destination of a dock, it is
169 enqueued for execution. Before the instruction executes, it may cause
170 the dock to wait for a packet to arrive at the dock's data destination
171 or for a value to be presented by the ship. When an instruction
172 executes it may consume this data and may present a data value to the
173 ship or transmit a packet.
175 When an instruction sends a packet into the switch fabric, it may
176 specify that the payload of the packet is irrelevant. Such packets
177 are known as {\it tokens}, and consume less energy than data packets.
181 \epsfig{file=overview-new,width=2.5in}\\
182 {\it Overview of a Fleet processor; dark gray shading represents the
183 switch fabric, ships are shown in light gray, and docks are shown in blue.}
189 \section{The FleetTwo Dock}
191 The diagram below represents a conceptual view of the interface
192 between ships and the switch fabric; actual implementation circuitry
196 \epsfig{file=all,width=3.5in}\\
197 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
198 blue lines carry either tokens or data words, red lines carry either
199 instructions or torpedoes, and dashed lines carry only tokens.}
202 Each dock consists of a {\it data latch}, which is as wide as a single
203 machine word and a {\it pump}, which is a circular fifo of
204 instruction-width latches. The values in the pump control the data
205 latch. The dock also includes a {\it path latch}, which
206 stores the path along which outgoing packets will be sent.\color{black}
208 Note that the pump in each dock has a destination of its own; this is
209 the {\it instruction destination} mentioned in the previous section.
211 From any source to any dock's data destination there are
212 two distinct paths which differ by a single bit. This bit is known as
213 the ``signal'' bit, and the routing of a packet is not affected by it;
214 the signal bit is used to pass control values between docks. Note that paths
215 terminating at an {\it instruction} destination need not have a signal
219 \section{Instructions}
221 In order to cause an instruction to execute, the programmer must first
222 arrange for that instruction word to arrive in the data latch of some
223 output dock. For example, this might be the ``data read'' output dock
224 of the memory access ship or the output of a fifo ship. Once an
225 instruction has arrived at this output dock, it is {\it dispatched} by
226 sending it to the {\it instruction port} of the dock at which it is to
229 Each instruction is 26 bits long, which makes it possible for an
230 instruction and an 11-bit path to fit in a single word of memory.
231 This path is the path from the {\it dispatching} dock to the {\it
234 \setlength{\bitwidth}{3.5mm}
236 \begin{bytefield}{37}
237 \bitheader[b]{0,10,11,36}\\
238 \bitbox{26}{instruction}
239 \bitbox{11}{dispatch path}
245 \subsection{Life Cycle of an Instruction}
247 The diagram below shows an input dock for purposes of illustration:
250 \epsfig{file=in,width=4in}\\
254 Note the mux on the path between {\tt EF} (epilogue fifo) and {\tt IF}
255 (instruction fifo); this is known as ``the hatch''. The hatch has two
256 states: sealed and unsealed. When the machine powers up, the hatch is
257 unsealed; it is sealed by the {\tt tail} instruction and unsealed
258 whenever the outer loop counter is set to zero (for any
259 reason\footnote{this includes {\tt OLC} being decremented to zero, a
260 {\tt set} instruction, or the occurrence
263 When an instruction arrives at the epilogue fifo ({\tt EF}), it waits
264 there until the hatch is in the unsealed state; the instruction then
265 enters the instruction fifo. When an instruction emerges from the
266 instruction fifo, it arrives at the ``on deck'' ({\tt OD}) stage,
267 where it may execute.
270 \epsfig{file=out,width=4in}\\
274 \subsubsection{Torpedoes}
276 A token sent to an instruction destination is called a {\it torpedo}.
277 When a torpedo arrives at the tail of {\tt EF}, it is deposited in a
278 waiting area (not shown) rather than being enqueued into {\tt EF}.
280 There is a latch (not shown) called the {\it torpedo acknowledgment path
281 latch} ({\tt TAPL}) which stores a path. When a torpedo is consumed
282 (see section ``On Deck''), a token is sent along the path held in this
285 \subsection{Format of an Instruction}
287 All instruction words have the following format:
289 \newcommand{\bitsHeader}{
294 \newcommand{\bitsHeaderNoI}{
300 \setlength{\bitwidth}{3.5mm}
302 \begin{bytefield}{37}
303 \bitheader[b]{0,10,11,31,32,34-36}\\
308 \bitbox{11}{dispatch path}
313 \item The {\tt I} bit stands for {\tt Interruptible}, and indicates if an
314 instruction is vulnerable to torpedoes. This bit only appears in {\tt move} instructions.
316 \item The {\tt OS} (``One Shot'') bit indicates whether or not this
317 instruction can pass through the pump more than once. If set to
318 {\tt 1}, then the instruction is a ``one-shot'' instruction, and
319 does not pass through the instruction fifo more than once.
321 \item The {\tt P} bits are a {\it predicate}; this
322 holds a code which indicates if the instruction should be executed or
323 ignored depending on the state of flags in the dock.
327 \subsection{Loop Counters}
329 A programmer can perform two types of loops: {\it inner} loops of only
330 one instruction and {\it outer} loops of multiple instructions. Inner
331 loops may be nested within an outer loop, but no other nesting of
334 The dock has two loop counters, one for each kind of loop:
337 \item {\tt OLC} is the Outer Loop Counter
338 \item {\tt ILC} is the Inner Loop Counter
341 The {\tt OLC} applies to all instructions and can hold integers {\tt
344 The {\tt ILC} applies only to {\tt move} instructions and can hold
345 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
346 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
347 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
348 executes until interrupted by a torpedo. After every {\tt move}
349 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
350 to {\tt 1}, {\it not to 0}).
353 \subsection{Flags and Predication}
355 The pump has three flags: {\tt A}, {\tt B}, and {\tt C}.
358 \item The {\tt A} and {\tt B} flags are general-purpose flags which
359 may be set and cleared by the programmer.
363 % The {\tt L} flag, known as the {\it last} flag, is set whenever
364 % the value in the outer counter ({\tt OLC}) is one,
367 % that the dock is in the midst of the last iteration of an
368 % outer loop. This flag can be used to perform certain
369 % operations (such as sending a completion token) only on the last
370 % iteration of an outer loop.
372 \item The {\tt C} flag is known as the {\it control} flag, and may be
373 set by the {\tt move} instruction based on information from the
374 ship or from an inbound packet. See the {\tt move} instruction
380 The {\tt P} field specifies a three-bit {\it predicate}. The
381 predicate determines which conditions must be true in order for the
382 instruction to execute; if it is not executed, it is simply {\it
383 ignored}. The table below shows what conditions must be true in
384 order for an instruction to execute:
387 \begin{tabular}{|r|ll|}\hline
388 Code & Execute & if \\\hline
389 {\tt 000:} & {\tt OLC$\neq$0} & and {\tt A=0} \\
390 {\tt 001:} & {\tt OLC$\neq$0} & and {\tt A=1} \\
391 {\tt 010:} & {\tt OLC$\neq$0} & and {\tt B=0} \\
392 {\tt 011:} & {\tt OLC$\neq$0} & and {\tt B=1} \\
393 {\tt 100:} & {\tt OLC$\neq$0} & and {\tt C=0} \\
394 {\tt 101:} & {\tt OLC$\neq$0} & and {\tt C=1} \\
395 {\tt 110:} & {\tt OLC$\neq$0} & \\
396 {\tt 111:} & always & \\
403 When an instruction arrives on deck, two concurrent processes are
404 started. No subsequent instruction may come on deck until both
405 processes have completed:
411 \item If the outer loop counter is zero ({\tt OLC=0}) or the
412 instruction on deck is a one-shot instruction ({\tt
414 \item {\it Otherwise} wait for the hatch to be sealed and
415 enqueue a copy of the instruction currently on deck.
422 If the instruction's predicate condition is not met (see
423 section on predicates), do nothing.
426 {\it Otherwise} if the instruction is interruptible ({\tt I=0})
427 and a torpedo is present in the waiting area: consume the
428 torpedo, set the outer loop counter to zero ({\tt OLC=0}),
429 \color{red}set the inner loop counter to one ({\tt ILC=1}),\color{black}\
430 unseal the hatch, and transmit a token along in the
431 {\it torpedo acknowledgment path latch} ({\tt TAPL}).
434 {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it
435 not} a {\tt move}: execute the instruction.
444 \section{Instructions}
446 The dock supports for instructions:
447 {\tt move} (variants: {\tt moveto}, {\tt dispatch}),
454 \subsection{{\tt move} (variants: {\tt moveto}, {\tt dispatch})}
456 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
458 \begin{bytefield}{26}
459 \bitheader[b]{14-20}\\
473 \begin{bytefield}{26}
474 \bitheader[b]{0,12,13}\\
475 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
478 \bitbox{13}{\tt Immediate}
481 \begin{bytefield}{26}
482 \bitheader[b]{11,12,13}\\
483 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:25]\to Path}})\ \ }
492 \begin{bytefield}{26}
493 \bitheader[b]{11,12,13}\\
494 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
505 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
506 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
507 \item {\tt Dc} - Data Capture: pulse the data latch.
508 \item {\tt Do} - Data Output: fill the data successor.
509 \item {\tt To} - Token Output: fill the token successor.
512 The data successor and token successor must both be empty in order for
513 a {\tt move} instruction to attempt execution.
515 Every time the {\tt move} instruction executes, the {\tt C} flag may
519 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
520 of the incoming packet if {\tt Di} or {\tt Ti} is set.
522 \item At an {\it output} dock the {\tt C} flag is set to a value
523 provided by the ship if the {\tt Di} bit is set, and to the
524 signal bit of the incoming packet if {\tt Di} is clear and {\tt
532 \subsection{{\tt set}}
534 The {\tt set} command is used to set or decrement the inner loop
535 counter, outer loop counter, and data latch.
537 \newcommand{\bitsSet}{
538 \setlength{\bitwidth}{5mm}
540 \begin{bytefield}{26}
541 \bitheader[b]{19-25}\\
551 \begin{bytefield}{26}
552 \bitheader[b]{0,5,11-18}\\
553 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
555 \bitbox{5}{\tt 10000}
558 \bitbox{6}{\tt Immediate}
561 \begin{bytefield}{26}
562 \bitheader[b]{11-18}\\
563 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
565 \bitbox{5}{\tt 10000}
570 \begin{bytefield}{26}
571 \bitheader[b]{11-18}\\
572 \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
574 \bitbox{5}{\tt 10000}
579 \begin{bytefield}{26}
580 \bitheader[b]{0,5,6,11-18}\\
581 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
583 \bitbox{5}{\tt 01000}
587 \bitbox{6}{\tt Immediate}
590 \begin{bytefield}{26}
591 \bitheader[b]{6,11-18}\\
592 \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
594 \bitbox{5}{\tt 01000}
601 \begin{bytefield}{26}
602 \bitheader[b]{11-18}\\
603 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
605 \bitbox{5}{\tt 01000}
610 \begin{bytefield}{26}
611 \bitheader[b]{0,12,13-18}\\
612 \bitbox[1]{6}{\raggedleft \footnotesize {\tt 0-Extended Immediate}\to{\tt Data Latch}}
614 \bitbox{5}{\tt 00100}
616 \bitbox{13}{\tt Immediate}
619 \begin{bytefield}{26}
620 \bitheader[b]{0,12,13-18}\\
621 \bitbox[1]{6}{\raggedleft \footnotesize {\tt 1-Extended Immediate}\to{\tt Data Latch}}
623 \bitbox{5}{\tt 00100}
625 \bitbox{13}{\tt Immediate}
628 \begin{bytefield}{26}
629 \bitheader[b]{0,5,6,11,14-18}\\
630 \bitbox[1]{6}{\raggedleft {\tt Update Flags}}
632 \bitbox{5}{\tt 00010}
634 \bitbox{6}{\tt nextA}
635 \bitbox{6}{\tt nextB}
638 \begin{bytefield}{26}
639 \bitheader[b]{0,12,14-18}\\
640 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt TAPL}}
642 \bitbox{5}{\tt 00001}
644 \bitbox{13}{\tt Immediate}
652 The FleetTwo implementation is likely to have an unarchitected
653 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
654 with the possibly-extended literal {\it at the time that the {\tt set}
655 instruction comes on deck}. This latch is then copied into the data
656 latch when a {\tt set Data Latch} instruction
657 executes\color{black}.
659 Each of the {\tt nextA} and {\tt nextB} fields has the following
660 structure, and indicates which old flag values should be logically
661 {\tt OR}ed together to produce the new flag value:
667 \bitbox{1}{${\text{\tt A}}$}
668 \bitbox{1}{$\overline{\text{\tt A}}$}
669 \bitbox{1}{${\text{\tt B}}$}
670 \bitbox{1}{$\overline{\text{\tt B}}$}
671 \bitbox{1}{${\text{{\tt C}\ }}$}
672 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
676 Each bit corresponds to one possible input; all inputs whose bits are
677 set are {\tt OR}ed together, and the resulting value is assigned to
678 the flag. Note that if none of the bits are set, the value assigned
679 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
680 OR}ing any flag with its complement, and that {\tt set Flags} can
681 be used to create a {\tt nop} (no-op) by setting each flag to itself.
687 \subsection{{\tt shift}}
689 \newcommand{\shiftImmediateSize}{19}
691 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
692 bits. When a {\tt shift} instruction is executed, this immediate is copied
693 into the least significant \shiftImmediateSize\ bits of the data latch,
694 and the remaining most significant bits of the data latch are loaded
695 with the value formerly in the least significant bits of the data latch.
696 In this manner, large literals can be built up by ``shifting'' them
697 into the data latch \shiftImmediateSize\ bits at a time.
699 \newcommand{\bitsShift}{
700 \setlength{\bitwidth}{5mm}
702 \begin{bytefield}{26}
703 \bitheader[b]{0,18-20}\\
710 \bitbox{\shiftImmediateSize}{Immediate}
715 The FleetTwo implementation is likely to have an unarchitected
716 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
717 with the literal {\it at the time that the {\tt shift} instruction
718 comes on deck}. This latch is then copied into the data latch when
719 the instruction executes.
723 \subsection{{\tt tail}}
725 \newcommand{\bitsTail}{
726 \setlength{\bitwidth}{5mm}
728 \begin{bytefield}{26}
729 \bitheader[b]{19-20}\\
740 When a {\tt tail} instruction reaches the hatch, it seals the hatch.
741 The {\tt tail} instruction does not enter the instruction fifo.
745 %\subsection{{\tt takeOuterLoopCounter}}
747 %\setlength{\bitwidth}{5mm}
749 %\begin{bytefield}{26}
750 % \bitheader[b]{16-19,21}\\
764 %This instruction copies the value in the outer loop counter {\tt OLC}
765 %into the least significant bits of the data latch and leaves all other
766 %bits of the data latch unchanged.
768 %\subsection{{\tt takeInnerLoopCounter}}
770 %\setlength{\bitwidth}{5mm}
772 %\begin{bytefield}{26}
773 % \bitheader[b]{16-19,21}\\
787 %This instruction copies the value in the inner loop counter {\tt ILC}
788 %into the least significant bits of the data latch and leaves all other
789 %bits of the data latch unchanged.
794 %%\subsection{{\tt interrupt}}
796 %%\setlength{\bitwidth}{5mm}
798 %\begin{bytefield}{26}
799 % \bitheader[b]{0,5,16-19,21}\\
810 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
811 %there for the {\tt OD} stage to be full with an instruction that has
812 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
813 %{\it will not execute}, but {\it may reloop} if the conditions for
815 %\footnote{The ability to interrupt an instruction yet have it reloop is very
816 %useful for processing chunks of data with a fixed size header and/or
817 %footer and a variable length body.}
820 %\subsection{{\tt massacre}}
822 %\setlength{\bitwidth}{5mm}
824 %\begin{bytefield}{26}
825 % \bitheader[b]{16-19,21}\\
837 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
838 %for the {\tt OD} stage to be full with an instruction that has the
839 %{\tt IM} bit set. When this occurs, all instructions in the
840 %instruction fifo (including {\tt OD}) are retired.
842 %\subsection{{\tt clog}}
844 %\setlength{\bitwidth}{5mm}
846 %\begin{bytefield}{26}
847 % \bitheader[b]{16-19,21}\\
859 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
860 %no more instructions will be executed until an {\tt unclog} is
863 %\subsection{{\tt unclog}}
865 %\setlength{\bitwidth}{5mm}
867 %\begin{bytefield}{26}
868 % \bitheader[b]{16-19,21}\\
874 % \bitbox[lrtb]{2}{11}
880 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
881 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
882 %instructions retire.
884 %Note that issuing an {\tt unclog} instruction to a dock which is not
885 %clogged and whose instruction fifo contains no {\tt clog} instructions
886 %will cause the dock to deadlock.
891 \section*{Instruction Encoding Map\color{black}}
893 \hspace{-1cm}{\tt shift}\\
896 \hspace{-1cm}{\tt set}\\
899 \hspace{-1cm}{\tt move}\\
902 \hspace{-1cm}{\tt tail}\\
909 \epsfig{file=all,height=5in,angle=90}
912 \subsection*{Input Dock}
913 \epsfig{file=in,width=8in,angle=90}
916 \subsection*{Output Dock}
917 \epsfig{file=out,width=8in,angle=90}
921 %\epsfig{file=ports,height=5in,angle=90}
924 %\epsfig{file=best,height=5in,angle=90}