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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
70 & \color{red} Fixed a few typos \\
71 & \color{red} Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\
72 & \color{red} Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\
74 & When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
75 & Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
77 & Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
78 & Reworked encoding of {\tt set} instruction \\
81 & Factored in Russell Kao's comments (thanks!)\\
82 & Added mechanism for setting C-flag from fabric even on outboxes\\
84 & Made {\tt OLC} test a predicate-controlled condition\\
85 & Rewrote ``on deck'' section \\
86 & Added ``{\tt unset}'' value for {\tt ILC}\\
87 & Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
90 & added comment about address-to-path ship \\
91 & changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
92 & changed the order of instructions in the encoding map \\
94 & added epilogue fifo to diagrams \\
95 & indicated that a token sent to the instruction port is treated as a torpedo \\
97 %& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
98 %& replaced {\tt literal} with {\tt shift} instruction \\
100 %& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
101 %& Removed ability to manually set the {\tt C} flag \\
102 %& Expanded predicate field to three bits \\
103 %& New literals scheme (via shifting) \\
104 %& Instruction encoding changes made at Ivan's request (for layout purposes) \\
105 %& Added summary of instruction encodings on last page \\
107 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
109 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
110 %& update table 3.1.2 \\
111 %& rename {\tt S} flag to {\tt C} \\
112 %& noted that {\tt setFlags} can be used as {\tt nop} \\
114 %& removed the {\tt L} flag (epilogues can now do this) \\
115 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
116 %& renamed {\tt data} instruction to {\tt literal} \\
117 %& renamed {\tt send} instruction to {\tt move} \\
119 %& added ``if its predicate is true'' to repeat count \\
120 %& added note that red wires do not contact ships \\
121 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
122 %& removed black dot from diagrams \\
123 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
124 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
125 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
126 %& added section ``Torpedo Details'' \\
127 %& removed {\tt torpedo} instruction \\
130 %& renamed loop+repeat to outer+inner (not in red) \\
131 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
132 %& rewrote ``inner and outer loops'' section \\
133 %& updated all diagrams \\
136 %& Moved address bits to the LSB-side of a 37-bit instruction \\
137 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
138 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
139 %& Created the {\tt Hold} field \\
140 %& Changed how ReLooping works \\
141 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
148 \epsfig{file=all,height=1.5in}
149 \epsfig{file=overview-new,height=1.5in}
154 \section{Overview of Fleet}
156 A Fleet processor is organized around a {\it switch fabric}, which is
157 a packet-switched network with reliable in-order delivery. The switch
158 fabric is used to carry data between different functional units,
159 called {\it ships}. Each ship is connected to the switch fabric by
160 one or more programmable elements known as {\it docks}.
162 A {\it path} specifies a route through the switch fabric from a
163 particular {\it source} to a particular {\it destination}. The
164 combination of a path and a single word to be delivered is called a
165 {\it packet}. The switch fabric carries packets from their sources to
166 their destinations. Each dock has two destinations: one for {\it
167 instructions} and one for {\it data}. A Fleet is programmed by
168 depositing instruction packets into the switch fabric with paths that
169 will lead them to instruction destinations of the docks at which they
172 When a packet arrives at the instruction destination of a dock, it is
173 enqueued for execution. Before the instruction executes, it may cause
174 the dock to wait for a packet to arrive at the dock's data destination
175 or for a value to be presented by the ship. When an instruction
176 executes it may consume this data and may present a data value to the
177 ship or transmit a packet.
179 When an instruction sends a packet into the switch fabric, it may
180 specify that the payload of the packet is irrelevant. Such packets
181 are known as {\it tokens}, and consume less energy than data packets.
185 \epsfig{file=overview-new,width=2.5in}\\
186 {\it Overview of a Fleet processor; dark gray shading represents the
187 switch fabric, ships are shown in light gray, and docks are shown in blue.}
193 \section{The FleetTwo Dock}
195 The diagram below represents a conceptual view of the interface
196 between ships and the switch fabric; actual implementation circuitry
200 \epsfig{file=all,width=3.5in}\\
201 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
202 blue lines carry either tokens or data words, red lines carry either
203 instructions or torpedoes, and dashed lines carry only tokens.}
206 Each dock consists of a {\it data latch}, which is as wide as a single
207 machine word and a {\it pump}, which is a circular fifo of
208 instruction-width latches. The values in the pump control the data
209 latch. The dock also includes a {\it path latch}, which
210 stores the path along which outgoing packets will be sent.\color{black}
212 Note that the pump in each dock has a destination of its own; this is
213 the {\it instruction destination} mentioned in the previous section.
215 From any source to any dock's data destination there are
216 two distinct paths which differ by a single bit. This bit is known as
217 the ``signal'' bit, and the routing of a packet is not affected by it;
218 the signal bit is used to pass control values between docks. Note that paths
219 terminating at an {\it instruction} destination need not have a signal
223 \section{Instructions}
225 In order to cause an instruction to execute, the programmer must first
226 arrange for that instruction word to arrive in the data latch of some
227 output dock. For example, this might be the ``data read'' output dock
228 of the memory access ship or the output of a fifo ship. Once an
229 instruction has arrived at this output dock, it is {\it dispatched} by
230 sending it to the {\it instruction port} of the dock at which it is to
233 Each instruction is 26 bits long, which makes it possible for an
234 instruction and an 11-bit path to fit in a single word of memory.
235 This path is the path from the {\it dispatching} dock to the {\it
238 \setlength{\bitwidth}{3.5mm}
240 \begin{bytefield}{37}
241 \bitheader[b]{0,10,11,36}\\
242 \bitbox{26}{instruction}
243 \bitbox{11}{dispatch path}
249 \subsection{Life Cycle of an Instruction}
251 The diagram below shows an input dock for purposes of illustration:
254 \epsfig{file=in,width=4in}\\
258 Note the mux on the path between {\tt EF} (epilogue fifo) and {\tt IF}
259 (instruction fifo); this is known as ``the hatch''. The hatch has two
260 states: sealed and unsealed. When the machine powers up, the hatch is
261 unsealed; it is sealed by the {\tt tail} instruction and unsealed
262 whenever the outer loop counter is set to zero (for any
263 reason\footnote{this includes {\tt OLC} being decremented to zero, a
264 {\tt set} instruction, or the occurrence
267 When an instruction arrives at the epilogue fifo ({\tt EF}), it waits
268 there until the hatch is in the unsealed state; the instruction then
269 enters the instruction fifo. When an instruction emerges from the
270 instruction fifo, it arrives at the ``on deck'' ({\tt OD}) stage,
271 where it may execute.
274 \epsfig{file=out,width=4in}\\
278 \subsubsection{Torpedoes}
280 A token sent to an instruction destination is called a {\it torpedo}.
281 When a torpedo arrives at the tail of {\tt EF}, it is deposited in a
282 waiting area (not shown) rather than being enqueued into {\tt EF}.
284 There is a latch (not shown) called the {\it torpedo acknowledgment path
285 latch} ({\tt TAPL}) which stores a path. When a torpedo is consumed
286 (see section ``On Deck''), a token is sent along the path held in this
289 \subsection{Format of an Instruction}
291 All instruction words have the following format:
293 \newcommand{\bitsHeader}{
298 \newcommand{\bitsHeaderNoI}{
304 \setlength{\bitwidth}{3.5mm}
306 \begin{bytefield}{37}
307 \bitheader[b]{0,10,11,31,32,34-36}\\
312 \bitbox{11}{dispatch path}
317 \item The {\tt I} bit stands for {\tt Interruptible}, and indicates if an
318 instruction is vulnerable to torpedoes. This bit only appears in {\tt move} instructions.
320 \item The {\tt OS} (``One Shot'') bit indicates whether or not this
321 instruction can pass through the pump more than once. If set to
322 {\tt 1}, then the instruction is a ``one-shot'' instruction, and
323 does not pass through the instruction fifo more than once.
325 \item The {\tt P} bits are a {\it predicate}; this
326 holds a code which indicates if the instruction should be executed or
327 ignored depending on the state of flags in the dock.
331 \subsection{Loop Counters}
333 A programmer can perform two types of loops: {\it inner} loops of only
334 one instruction and {\it outer} loops of multiple instructions. Inner
335 loops may be nested within an outer loop, but no other nesting of
338 The dock has two loop counters, one for each kind of loop:
341 \item {\tt OLC} is the Outer Loop Counter
342 \item {\tt ILC} is the Inner Loop Counter
345 The {\tt OLC} applies to all instructions and can hold integers {\tt
348 The {\tt ILC} applies only to {\tt move} instructions and can hold
349 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
350 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
351 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
352 executes until interrupted by a torpedo. After every {\tt move}
353 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
354 to {\tt 1}, {\it not to 0}).
357 \subsection{Flags and Predication}
359 The pump has three flags: {\tt A}, {\tt B}, and {\tt C}.
362 \item The {\tt A} and {\tt B} flags are general-purpose flags which
363 may be set and cleared by the programmer.
367 % The {\tt L} flag, known as the {\it last} flag, is set whenever
368 % the value in the outer counter ({\tt OLC}) is one,
371 % that the dock is in the midst of the last iteration of an
372 % outer loop. This flag can be used to perform certain
373 % operations (such as sending a completion token) only on the last
374 % iteration of an outer loop.
376 \item The {\tt C} flag is known as the {\it control} flag, and may be
377 set by the {\tt move} instruction based on information from the
378 ship or from an inbound packet. See the {\tt move} instruction
384 The {\tt P} field specifies a three-bit {\it predicate}. The
385 predicate determines which conditions must be true in order for the
386 instruction to execute; if it is not executed, it is simply {\it
387 ignored}. The table below shows what conditions must be true in
388 order for an instruction to execute:
391 \begin{tabular}{|r|ll|}\hline
392 Code & Execute & if \\\hline
393 {\tt 000:} & {\tt OLC$\neq$0} & and {\tt A=0} \\
394 {\tt 001:} & {\tt OLC$\neq$0} & and {\tt A=1} \\
395 {\tt 010:} & {\tt OLC$\neq$0} & and {\tt B=0} \\
396 {\tt 011:} & {\tt OLC$\neq$0} & and {\tt B=1} \\
397 {\tt 100:} & \color{red}Unused\color{black} & \\
398 {\tt 101:} & \color{red}Unused\color{black} & \\
399 {\tt 110:} & {\tt OLC$\neq$0} & \\
400 {\tt 111:} & always & \\
407 When an instruction arrives on deck, two concurrent processes are
408 started. No subsequent instruction may come on deck until both
409 processes have completed:
415 \item If the outer loop counter is zero ({\tt OLC=0}) or the
416 instruction on deck is a one-shot instruction ({\tt
418 \item {\it Otherwise} wait for the hatch to be sealed and
419 enqueue a copy of the instruction currently on deck.
426 If the instruction's predicate condition is not met (see
427 section on predicates), do nothing.
430 {\it Otherwise} if the instruction is interruptible ({\tt I=0})
431 and a torpedo is present in the waiting area: consume the
432 torpedo, set the outer loop counter to zero ({\tt OLC=0}),
433 set the inner loop counter to one ({\tt ILC=1}),
434 unseal the hatch, and transmit a token along in the
435 {\it torpedo acknowledgment path latch} ({\tt TAPL}).
438 {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it
439 not} a {\tt move}: execute the instruction.
448 \section{Instructions}
450 The dock supports \color{red}four\color{black}\ instructions:
451 {\tt move} (variants: {\tt moveto}, {\tt dispatch}),
458 \subsection{{\tt move} (variants: {\tt moveto}, {\tt dispatch})}
460 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
462 \begin{bytefield}{26}
463 \bitheader[b]{14-20}\\
477 \begin{bytefield}{26}
478 \bitheader[b]{0,12,13}\\
479 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
482 \bitbox{13}{\tt Immediate}
485 \begin{bytefield}{26}
486 \bitheader[b]{11,12,13}\\
487 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:25]\to Path}})\ \ }
496 \begin{bytefield}{26}
497 \bitheader[b]{11,12,13}\\
498 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
509 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
510 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
511 \item {\tt Dc} - Data Capture: pulse the data latch.
512 \item {\tt Do} - Data Output: fill the data successor.
513 \item {\tt To} - Token Output: fill the token successor.
516 The data successor and token successor must both be empty in order for
517 a {\tt move} instruction to attempt execution.
519 Every time the {\tt move} instruction executes, the {\tt C} flag may
523 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
524 of the incoming packet if {\tt Di} or {\tt Ti} is set.
526 \item At an {\it output} dock the {\tt C} flag is set to a value
527 provided by the ship if the {\tt Di} bit is set, and to the
528 signal bit of the incoming packet if {\tt Di} is clear and {\tt
536 \subsection{{\tt set}}
538 The {\tt set} command is used to set or decrement the inner loop
539 counter, outer loop counter, and data latch.
541 \newcommand{\bitsSet}{
542 \setlength{\bitwidth}{5mm}
544 \begin{bytefield}{26}
545 \bitheader[b]{19-25}\\
555 \begin{bytefield}{26}
556 \bitheader[b]{0,5,11-18}\\
557 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
559 \bitbox{5}{\tt 10000}
562 \bitbox{6}{\tt Immediate}
565 \begin{bytefield}{26}
566 \bitheader[b]{11-18}\\
567 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
569 \bitbox{5}{\tt 10000}
574 \begin{bytefield}{26}
575 \bitheader[b]{11-18}\\
576 \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
578 \bitbox{5}{\tt 10000}
583 \begin{bytefield}{26}
584 \bitheader[b]{0,5,6,11-18}\\
585 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
587 \bitbox{5}{\tt 01000}
591 \bitbox{6}{\tt Immediate}
594 \begin{bytefield}{26}
595 \bitheader[b]{6,11-18}\\
596 \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
598 \bitbox{5}{\tt 01000}
605 \begin{bytefield}{26}
606 \bitheader[b]{11-18}\\
607 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
609 \bitbox{5}{\tt 01000}
614 \begin{bytefield}{26}
615 \bitheader[b]{0,12,13-18}\\
616 \bitbox[1]{6}{\raggedleft \footnotesize {\tt 0-Extended Immediate}\to{\tt Data Latch}}
618 \bitbox{5}{\tt 00100}
620 \bitbox{13}{\tt Immediate}
623 \begin{bytefield}{26}
624 \bitheader[b]{0,12,13-18}\\
625 \bitbox[1]{6}{\raggedleft \footnotesize {\tt 1-Extended Immediate}\to{\tt Data Latch}}
627 \bitbox{5}{\tt 00100}
629 \bitbox{13}{\tt Immediate}
632 \begin{bytefield}{26}
633 \bitheader[b]{0,5,6,11,14-18}\\
634 \bitbox[1]{6}{\raggedleft {\tt Update Flags}}
636 \bitbox{5}{\tt 00010}
638 \bitbox{6}{\tt nextA}
639 \bitbox{6}{\tt nextB}
642 \begin{bytefield}{26}
643 \bitheader[b]{0,12,14-18}\\
644 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt TAPL}}
646 \bitbox{6}{\tt 000010}
647 \bitbox{13}{\tt Immediate}
651 \begin{bytefield}{26}
652 \bitheader[b]{0,12,14-18}\\
653 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt TAPL}}
655 \bitbox{6}{\tt 000001}
665 The FleetTwo implementation is likely to have an unarchitected
666 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
667 with the possibly-extended literal {\it at the time that the {\tt set}
668 instruction comes on deck}. This latch is then copied into the data
669 latch when a {\tt set Data Latch} instruction
670 executes\color{black}.
672 Each of the {\tt nextA} and {\tt nextB} fields has the following
673 structure, and indicates which old flag values should be logically
674 {\tt OR}ed together to produce the new flag value:
680 \bitbox{1}{${\text{\tt A}}$}
681 \bitbox{1}{$\overline{\text{\tt A}}$}
682 \bitbox{1}{${\text{\tt B}}$}
683 \bitbox{1}{$\overline{\text{\tt B}}$}
684 \bitbox{1}{${\text{{\tt C}\ }}$}
685 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
689 Each bit corresponds to one possible input; all inputs whose bits are
690 set are {\tt OR}ed together, and the resulting value is assigned to
691 the flag. Note that if none of the bits are set, the value assigned
692 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
693 OR}ing any flag with its complement, and that {\tt set Flags} can
694 be used to create a {\tt nop} (no-op) by setting each flag to itself.
700 \subsection{{\tt shift}}
702 \newcommand{\shiftImmediateSize}{19}
704 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
705 bits. When a {\tt shift} instruction is executed, this immediate is copied
706 into the least significant \shiftImmediateSize\ bits of the data latch,
707 and the remaining most significant bits of the data latch are loaded
708 with the value formerly in the least significant bits of the data latch.
709 In this manner, large literals can be built up by ``shifting'' them
710 into the data latch \shiftImmediateSize\ bits at a time.
712 \newcommand{\bitsShift}{
713 \setlength{\bitwidth}{5mm}
715 \begin{bytefield}{26}
716 \bitheader[b]{0,18-20}\\
723 \bitbox{\shiftImmediateSize}{Immediate}
728 The FleetTwo implementation is likely to have an unarchitected
729 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
730 with the literal {\it at the time that the {\tt shift} instruction
731 comes on deck}. This latch is then copied into the data latch when
732 the instruction executes.
736 \subsection{{\tt tail}}
738 \newcommand{\bitsTail}{
739 \setlength{\bitwidth}{5mm}
741 \begin{bytefield}{26}
742 \bitheader[b]{19-20}\\
753 When a {\tt tail} instruction reaches the hatch, it seals the hatch.
754 The {\tt tail} instruction does not enter the instruction fifo.
758 %\subsection{{\tt takeOuterLoopCounter}}
760 %\setlength{\bitwidth}{5mm}
762 %\begin{bytefield}{26}
763 % \bitheader[b]{16-19,21}\\
777 %This instruction copies the value in the outer loop counter {\tt OLC}
778 %into the least significant bits of the data latch and leaves all other
779 %bits of the data latch unchanged.
781 %\subsection{{\tt takeInnerLoopCounter}}
783 %\setlength{\bitwidth}{5mm}
785 %\begin{bytefield}{26}
786 % \bitheader[b]{16-19,21}\\
800 %This instruction copies the value in the inner loop counter {\tt ILC}
801 %into the least significant bits of the data latch and leaves all other
802 %bits of the data latch unchanged.
807 %%\subsection{{\tt interrupt}}
809 %%\setlength{\bitwidth}{5mm}
811 %\begin{bytefield}{26}
812 % \bitheader[b]{0,5,16-19,21}\\
823 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
824 %there for the {\tt OD} stage to be full with an instruction that has
825 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
826 %{\it will not execute}, but {\it may reloop} if the conditions for
828 %\footnote{The ability to interrupt an instruction yet have it reloop is very
829 %useful for processing chunks of data with a fixed size header and/or
830 %footer and a variable length body.}
833 %\subsection{{\tt massacre}}
835 %\setlength{\bitwidth}{5mm}
837 %\begin{bytefield}{26}
838 % \bitheader[b]{16-19,21}\\
850 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
851 %for the {\tt OD} stage to be full with an instruction that has the
852 %{\tt IM} bit set. When this occurs, all instructions in the
853 %instruction fifo (including {\tt OD}) are retired.
855 %\subsection{{\tt clog}}
857 %\setlength{\bitwidth}{5mm}
859 %\begin{bytefield}{26}
860 % \bitheader[b]{16-19,21}\\
872 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
873 %no more instructions will be executed until an {\tt unclog} is
876 %\subsection{{\tt unclog}}
878 %\setlength{\bitwidth}{5mm}
880 %\begin{bytefield}{26}
881 % \bitheader[b]{16-19,21}\\
887 % \bitbox[lrtb]{2}{11}
893 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
894 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
895 %instructions retire.
897 %Note that issuing an {\tt unclog} instruction to a dock which is not
898 %clogged and whose instruction fifo contains no {\tt clog} instructions
899 %will cause the dock to deadlock.
904 \section*{Instruction Encoding Map\color{black}}
906 \hspace{-1cm}{\tt shift}\\
909 \hspace{-1cm}{\tt set}\\
912 \hspace{-1cm}{\tt move}\\
915 \hspace{-1cm}{\tt tail}\\
922 \epsfig{file=all,height=5in,angle=90}
925 \subsection*{Input Dock}
926 \epsfig{file=in,width=8in,angle=90}
929 \subsection*{Output Dock}
930 \epsfig{file=out,width=8in,angle=90}
934 %\epsfig{file=ports,height=5in,angle=90}
937 %\epsfig{file=best,height=5in,angle=90}