2 projectname = bee2-control-user-fifo
4 build_machine = sting.eecs.berkeley.edu
5 build_machine_xilinx_path = /opt/xilinx/ISE9.2i_lin/
6 build_machine_work_dir = ~/$(projectname)
9 ## you probably want to customize the stuff above this line
11 ## you probably don't want to change anything below this line
13 xilinx = cd $(build_machine_work_dir);
14 xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
15 xilinx += XILINX=$(XILINX)
16 xilinx += PATH=$$PATH:$(XILINX)/bin/lin
17 xilinx += $(XILINX)/bin/lin/
19 bitfile = bee2-control-user-fifo.bit
21 remote_run = user_unprogram 1;
22 remote_run += user_program 1 $(bitfile);
23 remote_run += ./remote_run.pl;
24 remote_run += cat transcript;
26 verilog_files = $(find . -name \*.v)
28 run: upload build/fpga/$(bitfile)
29 ssh root@$(bee2_machine) '$(remote_run)'
31 upload: build/fpga/$(bitfile)
32 scp build/fpga/$(bitfile) root@$(bee2_machine):
34 build/fpga/$(bitfile): $(verilog_files)
36 rsync -zare --progress --delete --verbose ./ ${build_machine_work_dir}
37 time ssh ${build_machine} 'make -C ${build_machine_work_dir} synth XILINX=${build_machine_xilinx_path}'
38 cp main.bit build/fpga/$(bitfile)
39 scp remote_run.pl root@$(bee2_machine):
44 for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
47 rm -rf build/fpga/_ngo
48 $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
49 $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
50 $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
51 $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
52 $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
53 # $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf