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29 // The synopsys directives "translate_off/translate_on" specified below are
30 // supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
31 // tools. Ensure they are correct for your synthesis tool(s).
33 // You must compile the wrapper file async_fifo_8_8_128.v when simulating
34 // the core, async_fifo_8_8_128. When compiling the wrapper file, be sure to
35 // reference the XilinxCoreLib Verilog simulation library. For detailed
36 // instructions, please refer to the "CORE Generator Help".
40 module async_fifo_8_8_128(
63 output [7 : 0] rd_data_count;
64 output [7 : 0] wr_data_count;
66 // synopsys translate_off
68 FIFO_GENERATOR_V2_2 #(
71 2, // c_data_count_width
72 "BlankString", // c_default_value
74 "0", // c_dout_rst_val
77 "virtex2p", // c_family
78 0, // c_has_almost_empty
79 0, // c_has_almost_full
81 0, // c_has_data_count
82 0, // c_has_meminit_file
84 1, // c_has_rd_data_count
90 1, // c_has_wr_data_count
92 2, // c_implementation_type
93 0, // c_init_wr_pntr_val
95 "BlankString", // c_mif_file_name
96 0, // c_optimization_mode
98 0, // c_preload_latency
100 512, // c_prim_fifo_type
101 32, // c_prog_empty_thresh_assert_val
102 32, // c_prog_empty_thresh_negate_val
103 0, // c_prog_empty_type
104 96, // c_prog_full_thresh_assert_val
105 96, // c_prog_full_thresh_negate_val
106 0, // c_prog_full_type
107 8, // c_rd_data_count_width
109 7, // c_rd_pntr_width
110 0, // c_underflow_low
111 0, // c_use_fifo16_flags
114 8, // c_wr_data_count_width
116 7, // c_wr_pntr_width
117 1) // c_wr_response_latency
128 .RD_DATA_COUNT(rd_data_count),
129 .WR_DATA_COUNT(wr_data_count),
133 .PROG_EMPTY_THRESH(),
134 .PROG_EMPTY_THRESH_ASSERT(),
135 .PROG_EMPTY_THRESH_NEGATE(),
137 .PROG_FULL_THRESH_ASSERT(),
138 .PROG_FULL_THRESH_NEGATE(),
152 // synopsys translate_on