3 // Copyright (c) 2005-2006, Regents of the University of California
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without modification,
7 // are permitted provided that the following conditions are met:
9 // - Redistributions of source code must retain the above copyright notice,
10 // this list of conditions and the following disclaimer.
11 // - Redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer
13 // in the documentation and/or other materials provided with the
15 // - Neither the name of the University of California, Berkeley nor the
16 // names of its contributors may be used to endorse or promote
17 // products derived from this software without specific prior
18 // written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
21 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
24 // ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 // LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 // ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 //----------------------------------------------------------------------------
33 //----------------------------------------------------------------------------
39 // FIFO interface ports
40 WrFifo_Din, // Write FIFO data-in
41 WrFifo_WrEn, // Write FIFO write enable
42 WrFifo_Full, // Write FIFO full
43 WrFifo_WrCnt, // Write FIFO write count
44 RdFifo_Dout, // Read FIFO data-out
45 RdFifo_RdEn, // Read FIFO read enable
46 RdFifo_Empty, // Read FIFO empty
47 RdFifo_RdCnt, // Read FIFO read count
48 User_Rst, // User reset
49 User_Clk, // User clock
50 Sys_Rst, // System clock reset
51 Sys_Clk, // 100MHz system clock for CCLK generation
53 // SelectMAP interface ports
54 D_I, // Data bus input
55 D_O, // Data bus output
56 D_T, // Data bus tristate enable
57 RDWR_B, // Read/write signal
59 INIT_B, // Initialization/interrupt signal
63 // FIFO interface ports
64 input [0:7] WrFifo_Din;
67 output [0:7] WrFifo_WrCnt;
68 output [0:7] RdFifo_Dout;
71 output [0:7] RdFifo_RdCnt;
77 // SelectMAP protocol ports
87 // | _ \ ___ / _(_)_ __ (_) |_(_) ___ _ __ ___ //
88 // | | | |/ _ \ |_| | '_ \| | __| |/ _ \| '_ \/ __| //
89 // | |_| | __/ _| | | | | | |_| | (_) | | | \__ \ //
90 // |____/ \___|_| |_|_| |_|_|\__|_|\___/|_| |_|___/ //
93 //----------------------------------------------------------------------------
95 //----------------------------------------------------------------------------
97 wire [0:7] WrFifo_Dout;
100 wire [0:7] WrFifo_RdCnt;
101 wire [0:7] WrFifo_RdCnt_int;
102 wire [0:7] WrFifo_WrCnt_int;
105 wire [0:7] RdFifo_Din;
108 wire [0:7] RdFifo_WrCnt;
109 wire [0:7] RdFifo_WrCnt_int;
110 wire [0:7] RdFifo_RdCnt_int;
112 //----------------------------------------------------------------------------
114 //----------------------------------------------------------------------------
117 reg [0:7] D_I_reg; // synthesis attribute iob of D_I_reg is true;
118 reg [0:7] D_O_reg; // synthesis attribute iob of D_O_reg is true;
119 reg RDWR_B_reg; // synthesis attribute iob of RDWR_B_reg is true;
120 reg CS_B_reg; // synthesis attribute iob of CS_B_reg is true;
121 reg INIT_B_reg; // synthesis attribute iob of INIT_B_reg is true;
124 assign D_O = D_O_reg;
125 assign INIT_B = INIT_B_reg;
128 always @( posedge Sys_Clk )
131 RDWR_B_reg <= RDWR_B;
135 //----------------------------------------------------------------------------
136 // Generate CCLK and associated reset
137 //----------------------------------------------------------------------------
142 always @( posedge Sys_Clk )
144 CS_B_reg_dly <= CS_B_reg;
147 always @( posedge Sys_Clk )
151 else if (RDWR_B_reg && ~CS_B_reg)
155 always @( posedge Sys_Clk )
158 SYNC_done_dly <= 1'b0;
160 SYNC_done_dly <= SYNC_done;
163 always @( posedge Sys_Clk )
167 else if (~CS_B_reg && CS_B_reg_dly && CCLK)
173 // _____ ___ _____ ___ //
174 // | ___|_ _| ___/ _ \ ___ //
175 // | |_ | || |_ | | | / __| //
176 // | _| | || _|| |_| \__ \ //
177 // |_| |___|_| \___/|___/ //
179 // Write FIFO: The write is with respect to the user. The user writes data to this
180 // FIFO and the control side of SelectMAP reads the data.
182 // Read FIFO: The read is with respect to the user. The user reads data sent from the
183 // control side of SelectMAP.
186 //----------------------------------------------------------------------------
188 //----------------------------------------------------------------------------
189 assign RdFifo_WrEn = SYNC_done_dly && ~RDWR_B_reg && ~CS_B_reg && ~RdFifo_Full && CCLK;
190 assign RdFifo_Din = D_I_reg;
192 async_fifo_8_8_128 RdFifo( .din( RdFifo_Din ),
193 .dout( RdFifo_Dout ),
195 .rd_en( RdFifo_RdEn ),
197 .wr_en( RdFifo_WrEn ),
199 .empty( RdFifo_Empty ),
200 .full( RdFifo_Full ),
201 .rd_data_count( RdFifo_RdCnt_int ),
202 .wr_data_count( RdFifo_WrCnt_int ) );
204 assign RdFifo_WrCnt = 8'd129 - RdFifo_WrCnt_int;
205 assign RdFifo_RdCnt = RdFifo_RdCnt_int;
207 //----------------------------------------------------------------------------
209 //----------------------------------------------------------------------------
210 assign WrFifo_RdEn = SYNC_done_dly && RDWR_B_reg && ~CS_B_reg && ~WrFifo_Empty && CCLK;
212 async_fifo_8_8_128 WrFifo( .din( WrFifo_Din ),
213 .dout( WrFifo_Dout ),
215 .rd_en( WrFifo_RdEn ),
217 .wr_en( WrFifo_WrEn ),
219 .empty( WrFifo_Empty ),
220 .full( WrFifo_Full ),
221 .rd_data_count( WrFifo_RdCnt_int ),
222 .wr_data_count( WrFifo_WrCnt_int ) );
224 assign WrFifo_WrCnt = 8'd129 - WrFifo_WrCnt_int;
225 assign WrFifo_RdCnt = WrFifo_RdCnt_int;
227 // ____ _ _ __ __ _ ____ //
228 // / ___| ___| | ___ ___| |_| \/ | / \ | _ \ //
229 // \___ \ / _ \ |/ _ \/ __| __| |\/| | / _ \ | |_) | //
230 // ___) | __/ | __/ (__| |_| | | |/ ___ \| __/ //
231 // |____/ \___|_|\___|\___|\__|_| |_/_/ \_\_| //
234 //----------------------------------------------------------------------------
235 // SelectMAP control outputs
236 //----------------------------------------------------------------------------
237 wire [0:7] DataCnt = RDWR_B_reg ? WrFifo_RdCnt : RdFifo_WrCnt;
239 assign D_T = {8{(~RDWR_B & ~CS_B)}}; // stop driving if master is sending
241 always @( posedge Sys_Clk )
243 D_O_reg <= CS_B_reg ? DataCnt : WrFifo_Dout;
244 INIT_B_reg <= WrFifo_Empty;
247 //----------------------------------------------------------------------------
258 // SelectMAP interface ports
260 RDWR_B, // Read/write signal
262 INIT_B, // Initialization/interrupt signal
263 CCLK, // Local CCLK output
268 // User clock/reset ports
272 // SelectMAP protocol ports
284 wire [0:31] LoopData;
285 wire [0:31] LoopDataW;
296 reg [6:1] gpleds_reg;
298 // synthesis attribute tig of activate_r is yes;
300 // synthesis attribute tig of activate_a is yes;
303 wire [7:0] write_data;
307 wire [7:0] read_data;
309 wire [7:0] read_wire;
315 assign read_enable = read_enable_;
316 inout [33:0] terminal;
318 always @(posedge User_Clk) begin
319 if (!read_enable && !read_empty) begin
325 Maps_Bee2_Map0 map (.Clock(User_Clk),
327 ._BTN(~read_enable_),
328 .__TERMINAL_SynchronousLink_Pins(terminal));
330 //synthesis attribute LOC of terminal is "AT13,AR13,AV13,AU13,AW13,AY13,AL15,AL14,AV15,AU15,AY14,AY15,AM16,AL16,AP16,AN16,AR16,AT16,AV16,AU16,AL18,AL17,AM17,AN17,AR17,AP17,AU17,AT17,AW16,AW17,AN18,AM18,AT18,AR18"
334 OBUF obuf_cclk( .I( CCLK_int ),
338 IOBUF iobuf_d0( .I( D_O[0] ),
344 IOBUF iobuf_d1( .I( D_O[1] ),
350 IOBUF iobuf_d2( .I( D_O[2] ),
356 IOBUF iobuf_d3( .I( D_O[3] ),
362 IOBUF iobuf_d4( .I( D_O[4] ),
368 IOBUF iobuf_d5( .I( D_O[5] ),
374 IOBUF iobuf_d6( .I( D_O[6] ),
380 IOBUF iobuf_d7( .I( D_O[7] ),
386 // Clock buffer and reset
387 IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ),
398 defparam rst0.INIT = 1'b1;
400 FD rst1( .D( rst[0] ),
404 defparam rst1.INIT = 1'b1;
406 FD rst2( .D( rst[1] ),
410 defparam rst2.INIT = 1'b1;
412 FD rst3( .D( rst[2] ),
416 defparam rst3.INIT = 1'b1;
418 assign User_Rst = |rst;
421 // FIFO module instantiation
423 .WrFifo_Din( write_data ),
424 .WrFifo_WrEn( write_enable ),
425 .WrFifo_Full( write_full ),
427 .RdFifo_Dout( read_data ),
428 .RdFifo_RdEn( read_enable ),
429 .RdFifo_Empty( read_empty ),
431 .User_Rst( User_Rst ),
432 .User_Clk( User_Clk ),
433 .Sys_Rst( User_Rst ),
434 .Sys_Clk( User_Clk ),