chips/marina/electric/arbiterM.delib/arbiter2.lay

   1 HarbiterM|8.10k
   2
   3 # Cell arbiter2;1{lay}
   4 Carbiter2;1{lay}||cmos90|1188748831546|1241981698008||ATTR_NCC(D5G3;NTY140;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981714344
   5 Ihalf2inArb;1{lay}|halfArb@4||0|-72|||D5G4;
   6 Ihalf2inArb;1{lay}|halfArb@5||0|72|Y||D5G4;
   7 NMetal-1-Pin|pin@44||6|4||||
   8 NMetal-1-Pin|pin@45||12|4||||
   9 NMetal-1-Pin|pin@46||12|-4||||
  10 NMetal-1-Pin|pin@47||18|-4||||
  11 Ametal-1|net@77|||S2700|halfArb@4|cross|6|-15|pin@44||6|4
  12 Ametal-1|net@78|||S1800|pin@44||6|4|pin@45||12|4
  13 Ametal-1|net@79|||S2700|pin@45||12|4|halfArb@5|inA|12|15
  14 Ametal-1|net@80|||S2700|halfArb@4|inA|12|-15|pin@46||12|-4
  15 Ametal-1|net@81|||S1800|pin@46||12|-4|pin@47||18|-4
  16 Ametal-1|net@84|||S2700|pin@47||18|-4|halfArb@5|cross_1|18|15
  17 Egnd||D5G2;|halfArb@5|gnd|G
  18 Egnd_1||D5G2;|halfArb@5|gnd_1|G
  19 Egnd_2||D5G2;|halfArb@4|gnd|G
  20 Egnd_3||D5G2;|halfArb@4|gnd_1|G
  21 Egrant[A]||D5G2;|halfArb@4|grant[B]|O
  22 Egrant[B]||D5G2;|halfArb@5|grant[B]|O
  23 Ereq[A]||D5G2;|halfArb@4|req[B]|I
  24 Ereq[B]||D5G2;|halfArb@5|req[B]|I
  25 Evdd||D5G2;|halfArb@5|vdd|P
  26 Evdd_1||D5G2;|halfArb@5|vdd_1|P
  27 Evdd_2||D5G2;|halfArb@5|vdd_2|P
  28 Evdd_3||D5G2;|halfArb@5|vdd_3|P
  29 Evdd_4||D5G2;|halfArb@4|vdd|P
  30 Evdd_5||D5G2;|halfArb@4|vdd_1|P
  31 Evdd_6||D5G2;|halfArb@4|vdd_2|P
  32 Evdd_7||D5G2;|halfArb@4|vdd_3|P
  33 X