chips/marina/electric/arbiterM.delib/arbiter3.lay

   1 HarbiterM|8.10k
   2
   3 # Cell arbiter3;1{lay}
   4 Carbiter3;1{lay}||cmos90|1225193389429|1238257435226||ATTR_NCC(D5G3;NTY140;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 Ihalf3inArbX;1{lay}|half3inA@0||0|72|||D5G4;
   7 Ihalf3inArbY;2{lay}|half3inA@2||0|-72|Y||D5G4;
   8 NMetal-1-Pin|pin@4||44.5|-8||||
   9 Ametal-1|net@5|||S1800|half3inA@2|cross|36.5|-8|pin@4||44.5|-8
  10 Ametal-1|net@6|||S2700|pin@4||44.5|-8|half3inA@0|inC|44.5|9
  11 Ametal-1|net@9|||S900|half3inA@0|cross|15|9|half3inA@2|inC|15|-8
  12 Egnd||D5G2;|half3inA@0|gnd|G
  13 Egnd_1||D5G2;|half3inA@0|gnd_1|G
  14 Egnd_2||D5G2;|half3inA@2|gnd|G
  15 Egnd_3||D5G2;|half3inA@2|gnd_1|G
  16 Egrant[A]||D5G2;|half3inA@0|grant[A]|O
  17 Egrant[A_1]@475263770|grant[A_1]|D5G2;|half3inA@0|grant[A_1]|O
  18 Egrant[A_1]|grant[B]|D5G2;|half3inA@2|grant[A]|O
  19 Ereq[A1]||D5G2;|half3inA@0|inB|I
  20 Ereq[A2]||D5G2;|half3inA@0|inA|I
  21 Ereq[A_2]|req[B1]|D5G2;|half3inA@2|req[A1]|I
  22 Ereq[A_3]|req[B2]|D5G2;|half3inA@2|req[A2]|I
  23 Evdd||D5G2;|half3inA@0|vdd|P
  24 Evdd_1||D5G2;|half3inA@0|vdd_1|P
  25 Evdd_2||D5G2;|half3inA@0|vdd_2|P
  26 Evdd_3||D5G2;|half3inA@0|vdd_3|P
  27 Evdd_4||D5G2;|half3inA@2|vdd|P
  28 Evdd_5||D5G2;|half3inA@2|vdd_1|P
  29 Evdd_6||D5G2;|half3inA@2|vdd_2|P
  30 Evdd_7||D5G2;|half3inA@2|vdd_3|P
  31 X