chips/marina/electric/arbiterM.delib/half2inArb.sch

   1 HarbiterM|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LredFive|redFive
   8
   9 # Cell half2inArb;1{sch}
  10 Chalf2inArb;1{sch}||schematic|1188747897929|1240453455444|
  11 IorangeTSMC090nm:PMOSx;1{ic}|NMOSx@0||11|-7.5|Y||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S10
  12 IorangeTSMC090nm:NMOSx;1{ic}|PMOSx@0||11|-18.5|Y||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S10
  13 Ngeneric:Facet-Center|art@0||0|0||||AV
  14 NOff-Page|conn@0||-9|-12.5|||YR|
  15 NOff-Page|conn@1||16|-13|||Y|
  16 NOff-Page|conn@2||-19|-7.5|||Y|
  17 NOff-Page|conn@3||3|-12|||YRRR|
  18 Ihalf2inArb;1{ic}|halfArb@2||18.5|4|||D5G4;
  19 IredFive:nand2;1{ic}|nor2n@0||-4|-24|Y||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S25|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  20 Ngeneric:Invisible-Pin|pin@0||-8|23|||||ART_message(D5G6;)Shalf2inArb
  21 Ngeneric:Invisible-Pin|pin@1||-9|14|||||ART_message(D5G3;)Sies 12 September 2007
  22 Ngeneric:Invisible-Pin|pin@2||-10|18|||||ART_message(D5G4;)Shalf of the arbier
  23 NWire_Pin|pin@6||-9|-23|||Y|
  24 NWire_Pin|pin@8||3|-24|||Y|
  25 NWire_Pin|pin@17||11|-24|||Y|
  26 NWire_Pin|pin@18||-9|-18.5|||Y|
  27 NWire_Pin|pin@19||11|-13|||Y|
  28 NWire_Pin|pin@21||-15|-25|||Y|
  29 NWire_Pin|pin@22||-15|-7.5|||Y|
  30 Ngeneric:Invisible-Pin|pin@23||-21|9|||||ART_message(D3G2;)S["The cross connection, inA,",is near ground to improve,the uncontested delay at,the price of greater delay,for metastability exit.]
  31 NPower|pwr@0||11|-2||||
  32 Awire|net@4|||0|nor2n@0|ina|-6.5|-23|pin@6||-9|-23
  33 Awire|net@5|||2700|pin@6||-9|-23|pin@18||-9|-18.5
  34 Awire|net@8|||1800|nor2n@0|out|-1.5|-24|pin@8||3|-24
  35 Awire|net@26|||1800|pin@8||3|-24|pin@17||11|-24
  36 Awire|net@27|||2700|pin@17||11|-24|PMOSx@0|d|11|-20.5
  37 Awire|net@30|||0|PMOSx@0|g|8|-18.5|pin@18||-9|-18.5
  38 Awire|net@31|||900|conn@0|y|-9|-14.5|pin@18||-9|-18.5
  39 Awire|net@32|||900|pin@19||11|-13|PMOSx@0|s|11|-16.5|SIM_verilog_wire_type(D5G2;)Strireg
  40 Awire|net@34|||900|NMOSx@0|s|11|-9.5|pin@19||11|-13
  41 Awire|net@35|||0|conn@1|a|14|-13|pin@19||11|-13
  42 Awire|net@37|||2700|pin@8||3|-24|conn@3|a|3|-14
  43 Awire|net@38|||900|pin@22||-15|-7.5|pin@21||-15|-25
  44 Awire|net@41|||0|nor2n@0|inb|-6.5|-25|pin@21||-15|-25
  45 Awire|net@43|||0|NMOSx@0|g|8|-7.5|pin@22||-15|-7.5
  46 Awire|net@49|||900|pwr@0||11|-2|NMOSx@0|d|11|-5.5
  47 Awire|net@50|||1800|conn@2|y|-17|-7.5|pin@22||-15|-7.5
  48 Ecross||D6G2;|conn@3|y|O
  49 Egrant[B]||D6G2;|conn@1|y|O
  50 EinA||D4G2;|conn@0|a|I
  51 Ereq[B]||D4G2;|conn@2|a|I
  52 X