chips/marina/electric/centersJ.delib/ctrAND5in30A.sch

   1 HcentersJ|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LredFive|redFive
   8
   9 # Cell ctrAND5in30A;1{sch}
  10 CctrAND5in30A;1{sch}||schematic|1188767434401|1206305495043||LEDRIVE_nand2@0()F41.56108|LEDRIVE_nand2@1()F41.56108|LEDRIVE_nor2n@0.nor2()F48.696438
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||14|0||||
  13 NOff-Page|conn@1||-36|-7|||Y|
  14 NOff-Page|conn@2||-36|-5|||Y|
  15 NOff-Page|conn@3||-36|-1|||Y|
  16 NOff-Page|conn@4||-36|1|||Y|
  17 NOff-Page|conn@5||-36|6|||Y|
  18 IredFive:inv;1{ic}|inv@1||6|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  19 IredFive:nand2n_sy;1{ic}|nand2@0||-30|-6|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2.5;)I100|ATTR_X(D5G1.5;NPX2;Y2.5;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  20 IredFive:nor2_sy;1{ic}|nand2@1||-30|0|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(T)I-1
  21 IctrAND5in30A;1{ic}|nand3and@0||10.5|11.5|||D5G4;
  22 IredFive:nand3;1{ic}|nor2n@0||-12.5|0|Y||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5G1.5;NPX3;Y2.5;)S15|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  23 Ngeneric:Invisible-Pin|pin@0||-13.5|27.5|||||ART_message(D5G5;)SctrAND5in30A
  24 Ngeneric:Invisible-Pin|pin@1||-13|23.5|||||ART_message(D5G3;)Sies 23 March 2008
  25 Ngeneric:Invisible-Pin|pin@2||-15|19.5|||||ART_message(D5G2;)S[this is the common part of 4 processes,one of which might be ignored]
  26 NWire_Pin|pin@28||-17|-6||||
  27 NWire_Pin|pin@29||-17|-2||||
  28 NWire_Pin|pin@34||-15.5|0||||
  29 NWire_Pin|pin@35||-17|2||||
  30 NWire_Pin|pin@36||-17|6||||
  31 IorangeTSMC090nm:wire90;1{ic}|wire90@0||-23|0|||D0G4;|ATTR_L(D5G1;PUD)S569|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  32 IorangeTSMC090nm:wire90;1{ic}|wire90@1||-3|0|||D0G4;|ATTR_L(D5G1;PUD)S958|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  33 IorangeTSMC090nm:wire90;1{ic}|wire90@2||-23|-6|||D0G4;|ATTR_L(D5G1;PUD)S569|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  34 Awire|net@3|||1800|wire90@1|b|-0.5|0|inv@1|in|3.5|0
  35 Awire|net@6|||1800|inv@1|out|8.5|0|conn@0|a|12|0
  36 Awire|net@58|||1800|wire90@2|b|-20.5|-6|pin@28||-17|-6
  37 Awire|net@59|||2700|pin@28||-17|-6|pin@29||-17|-2
  38 Awire|net@61|||1800|nand2@0|out|-27.5|-6|wire90@2|a|-25.5|-6
  39 Awire|net@64|||1800|nand2@1|out|-27.5|0|wire90@0|a|-25.5|0
  40 Awire|net@67|||0|wire90@1|a|-5.5|0|nor2n@0|out|-10|0
  41 Awire|net@78|||1800|conn@4|y|-34|1|nand2@1|inb|-32.5|1
  42 Awire|net@79|||0|nand2@0|ina|-32.5|-7|conn@1|y|-34|-7
  43 Awire|net@80|||0|nand2@0|inb|-32.5|-5|conn@2|y|-34|-5
  44 Awire|net@81|||0|nand2@1|ina|-32.5|-1|conn@3|y|-34|-1
  45 Awire|net@84|||1800|pin@29||-17|-2|nor2n@0|inc|-15|-2
  46 Awire|net@85|||0|nor2n@0|ina|-15|2|pin@35||-17|2
  47 Awire|net@86|||2700|pin@35||-17|2|pin@36||-17|6
  48 Awire|net@90|||0|pin@36||-17|6|conn@5|y|-34|6
  49 Awire|net@92|||0|pin@34||-15.5|0|wire90@0|b|-20.5|0
  50 EinA||D4G2;|conn@1|a|I
  51 EinB||D4G2;|conn@2|a|I
  52 EinC||D4G2;|conn@3|a|I
  53 EinD||D4G2;|conn@4|a|I
  54 EinD_1|inE|D4G2;|conn@5|a|I
  55 Eout||D6G2;|conn@0|y|O
  56 X