chips/marina/electric/driversM.delib/latchAndDriver60.lay

   1 HdriversM|8.10k
   2
   3 # External Libraries:
   4
   5 Lgates1inM|gates1inM
   6
   7 Lgates2inM|gates2inM
   8
   9 # Cell latchAndDriver60;1{lay}
  10 ClatchAndDriver60;1{lay}||cmos90|1195047322016|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241982205540
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 Igates1inM:inv60;1{lay}|inv60@1||4.5|0|Y||D5G4;
  13 Igates2inM:nand20;2{lay}|nand20@1||-47.5|0|||D5G4;
  14 NMetal-1-Pin|pin@2||-33.5|25||||
  15 NMetal-1-Pin|pin@3||-33.5|-25||||
  16 Ametal-2|net@7|||S0|nand20@1|gnd_1|-15|0|inv60@1|gnd|-24|0
  17 Ametal-2|net@8|||S0|nand20@1|vdd_2|-15|50|inv60@1|vdd_1|-24|50
  18 Ametal-2|net@9|||S0|nand20@1|vdd_3|-15|-50|inv60@1|vdd|-24|-50
  19 Ametal-1|net@10|||S2700|nand20@1|out|-33.5|-7|pin@2||-33.5|25
  20 Ametal-1|net@11|||S1800|pin@2||-33.5|25|inv60@1|inA|-16.5|25
  21 Ametal-1|net@12|||S900|nand20@1|out|-33.5|-7|pin@3||-33.5|-25
  22 Ametal-1|net@13|||S1800|pin@3||-33.5|-25|inv60@1|inB|-16.5|-25
  23 Egnd||D5G2;|inv60@1|gnd_1|G
  24 Egnd_1||D5G2;|nand20@1|gnd|G
  25 EinA||D5G2;|nand20@1|inA|I
  26 EinB||D5G2;|nand20@1|inB|I
  27 Eout||D5G2;|inv60@1|out|O
  28 Evdd||D5G2;|inv60@1|vdd_3|P
  29 Evdd_1||D5G2;|nand20@1|vdd_1|P
  30 Evdd_5||D5G2;|inv60@1|vdd_2|P
  31 Evdd_6||D5G2;|nand20@1|vdd|P
  32 X