chips/marina/electric/driversM.delib/predDri10wMC.sch

   1 HdriversM|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LredFive|redFive
   8
   9 # Cell predDri10wMC;1{sch}
  10 CpredDri10wMC;1{sch}||schematic|1188777360591|1244175568868||ATTR_verilog_template(D5G1;NTX5;Y-16;)Stranif1 #(100) ($(pred), gnd, $(in)); tranif1 #(100) ($(pred), gnd, $(mc)); wire $(node_name); not #(100) ($(node_name), $(pred)); rtranif0 #(100) ($(pred), vdd, $(node_name));
  11 IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@0||0|-6|||D0G4;|ATTR_Delay(D5G1;NPX-2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX-0.5;Y2.5;)S10
  12 IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@1||8.5|-6.5|X||D0G4;|ATTR_Delay(D5G1;NPX-2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX-0.5;Y2.5;)S4
  13 Ngeneric:Facet-Center|art@0||0|0||||AV
  14 NOff-Page|conn@0||-12|0||||
  15 NOff-Page|conn@1||27.5|0||||
  16 NOff-Page|conn@2||28|-6.5|||RR|
  17 NGround|gnd@0||0|-13||||
  18 NGround|gnd@1||8.5|-13||||
  19 IredFive:invLT;1{ic}|invLT@0||16|10|X||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S3|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  20 Ngeneric:Invisible-Pin|pin@0||9|42.5|||||ART_message(D5G6;)SpredDri10wMC
  21 Ngeneric:Invisible-Pin|pin@1||8.5|27|||||ART_message(D5G3;)Sies 20 April 2009
  22 Ngeneric:Invisible-Pin|pin@2||7.5|35|||||ART_message(D5G4;)S[predecessor driver size 10,with Master Clear]
  23 NWire_Pin|pin@4||0|0||||
  24 NWire_Pin|pin@15||-6|-6||||
  25 NWire_Pin|pin@16||-6|0||||
  26 NWire_Pin|pin@21||21|10||||
  27 NWire_Pin|pin@34||8.5|0||||
  28 Ngeneric:Invisible-Pin|pin@35||-18|6.5|||||ART_message(D5G4;)SHI is full
  29 NWire_Pin|pin@38||21|0||||
  30 NWire_Pin|pin@42||15|-6.5||||
  31 NWire_Pin|pin@56||-6|14||||
  32 NWire_Pin|pin@57||-3|2||||
  33 NWire_Pin|pin@58||15|2||||
  34 IredFive:pms3;1{ic}|pms3@0||0|14|||D5G4;|ATTR_Delay(D5G1;NPX-3;Y-1;)I100|ATTR_X(D5G1.5;NPX2.75;Y3;)S1
  35 IpredDri10wMC;1{ic}|predDri1@0||31|22|||D5G4;
  36 IorangeTSMC090nm:wire90;1{ic}|wire90@0||8|10|||D0G4;|ATTR_L(D5G1;PUD)D106.69999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  37 Awire|net@25|||900|pin@16||-6|0|pin@15||-6|-6
  38 Awire|net@61|||0|pin@16||-6|0|conn@0|y|-10|0
  39 Awire|net@70|||1800|invLT@0|in|18.5|10|pin@21||21|10
  40 Awire|net@72|||900|pin@21||21|10|pin@38||21|0
  41 Awire|net@91|||900|NMOSx@0|s|0|-8|gnd@0||0|-11
  42 Awire|net@97|||900|pin@4||0|0|NMOSx@0|d|0|-4
  43 Awire|net@98|||1800|pin@15||-6|-6|NMOSx@0|g|-3|-6
  44 Awire|net@102|||900|NMOSx@1|s|8.5|-8.5|gnd@1||8.5|-11
  45 Awire|net@104|||2700|NMOSx@1|d|8.5|-4.5|pin@34||8.5|0
  46 Awire|net@105|||1800|pin@34||8.5|0|pin@38||21|0
  47 Awire|net@106|||1800|pin@4||0|0|pin@34||8.5|0
  48 Awire|net@112|||1800|pin@38||21|0|conn@1|a|25.5|0
  49 Awire|net@117|||1800|pin@42||15|-6.5|conn@2|y|26|-6.5
  50 Awire|net@121|||1800|NMOSx@1|g|11.5|-6.5|pin@42||15|-6.5
  51 Awire|net@145|||0|invLT@0|out|13.5|10|wire90@0|b|10.5|10
  52 Awire|net@156|||2700|pin@42||15|-6.5|pin@58||15|2
  53 Awire|net@174|||2700|pin@4||0|0|pms3@0|d|0|4
  54 Awire|net@180|||0|wire90@0|a|5.5|10|pms3@0|g2|3|10
  55 Awire|net@182|||1800|pin@56||-6|14|pms3@0|g|-3|14
  56 Awire|net@183|||2700|pin@16||-6|0|pin@56||-6|14
  57 Awire|net@184|||900|pms3@0|g3|-3|6|pin@57||-3|2
  58 Awire|net@186|||1800|pin@57||-3|2|pin@58||15|2
  59 Ein||D4G2;|conn@0|a|I
  60 Emc||D4G2;|conn@2|a|I
  61 Epred||D6G2;|conn@1|y|O
  62 X