chips/marina/electric/driversM.delib/sucDri60cross.lay

   1 HdriversM|8.10k
   2
   3 # External Libraries:
   4
   5 Lgates2inM|gates2inM
   6
   7 # Cell sucDri60cross;1{lay}
   8 CsucDri60cross;1{lay}||cmos90|1230754463254|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
   9 Igates2inM:andOrInvert15;3{lay}|andOrInv@0||-32.5|0|||D5G4;
  10 Ngeneric:Facet-Center|art@0||0|0||||AV
  11 NMetal-1-Pin|pin@0||40.1|18||||
  12 IsucDri60plain;1{lay}|sucDri60@0||64.5|0|||D5G4;
  13 Ametal-2|net@0|||S0|sucDri60@0|gnd|32|0|andOrInv@0|gnd_1|32|0
  14 Ametal-2|net@1|||S0|sucDri60@0|vdd|32|50|andOrInv@0|vdd_2|32|50
  15 Ametal-2|net@2|||S0|sucDri60@0|vdd_1|32|-50|andOrInv@0|vdd_3|32|-50
  16 Ametal-1|net@3|||S1800|andOrInv@0|out|27.5|18|pin@0||40.1|18
  17 Ametal-1|net@4|||S900|pin@0||40.1|18|sucDri60@0|in|40.1|13
  18 EAbar||D5G2;|andOrInv@0|Abar|O
  19 EAtoD||D5G2;|andOrInv@0|AtoD|I
  20 EBbar||D5G2;|andOrInv@0|Bbar|O
  21 EBtoD||D5G2;|andOrInv@0|BtoD|I
  22 Efire[A]||D5G2;|andOrInv@0|fire[A]|I
  23 Efire[B]||D5G2;|andOrInv@0|fire[B]|I
  24 Egnd||D5G2;|andOrInv@0|gnd|G
  25 Egnd_1||D5G2;|sucDri60@0|gnd_1|G
  26 Esucc||D5G2;|sucDri60@0|succ|O
  27 Esucc_1||D5G2;|sucDri60@0|succ_1|O
  28 Esucc_2||D5G2;|sucDri60@0|succ_2|O
  29 Evdd||D5G2;|andOrInv@0|vdd|P
  30 Evdd_1||D5G2;|andOrInv@0|vdd_1|P
  31 Evdd_2||D5G2;|sucDri60@0|vdd_2|P
  32 Evdd_3||D5G2;|sucDri60@0|vdd_3|P
  33 X