chips/marina/electric/fillM.delib/fill2to9GNDctr.lay

   1 HfillM|8.10k
   2
   3 # Cell fill2to9GNDctr;1{lay}
   4 Cfill2to9GNDctr;1{lay}||cmos90|1239627726608|1240848417057||DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1243262533078
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 Ifill4to9;1{lay}|fill4to9@0||0|0|||D5G4;
   7 Ifill234GNDctr;2{lay}|fill234G@0||0|0|||D5G4;
   8 Ametal-4|net@0|||S0|fill234G@0|vdd_4|-72|36|fill4to9@0|vdd_8|-72|36
   9 Ametal-4|net@1|||S0|fill4to9@0|gnd_9|72|-36|fill234G@0|gnd_3|72|-36
  10 Ametal-4|net@2|||S0|fill4to9@0|gnd_8|-72|-36|fill234G@0|gnd_5|-72|-36
  11 Ametal-4|net@3|||S0|fill4to9@0|vdd_9|72|36|fill234G@0|vdd_1|72|36
  12 Ametal-4|net@4|||S0|fill234G@0|vdd_4|-72|36|fill4to9@0|vdd_8|-72|36
  13 Egnd||D5G2;|fill4to9@0|gnd|G
  14 Egnd_1||D5G2;|fill4to9@0|gnd_1|G
  15 Egnd_2||D5G2;|fill4to9@0|gnd_2|G
  16 Egnd_3||D5G2;|fill4to9@0|gnd_3|G
  17 Egnd_4||D5G2;|fill4to9@0|gnd_4|G
  18 Egnd_5||D5G2;|fill4to9@0|gnd_5|G
  19 Egnd_6||D5G2;|fill4to9@0|gnd_6|G
  20 Egnd_7||D5G2;|fill4to9@0|gnd_7|G
  21 Egnd_8||D5G2;|fill234G@0|gnd|G
  22 Egnd_9||D5G2;|fill234G@0|gnd_1|G
  23 Egnd_10||D5G2;|fill234G@0|gnd_2|G
  24 Egnd_11||D5G2;|fill234G@0|gnd_4|G
  25 Evdd||D5G2;|fill4to9@0|vdd|P
  26 Evdd_1||D5G2;|fill4to9@0|vdd_1|P
  27 Evdd_2||D5G2;|fill4to9@0|vdd_2|P
  28 Evdd_3||D5G2;|fill4to9@0|vdd_3|P
  29 Evdd_4||D5G2;|fill4to9@0|vdd_4|P
  30 Evdd_5||D5G2;|fill4to9@0|vdd_5|P
  31 Evdd_6||D5G2;|fill4to9@0|vdd_6|P
  32 Evdd_7||D5G2;|fill4to9@0|vdd_7|P
  33 Evdd_8||D5G2;|fill234G@0|vdd|P
  34 Evdd_9||D5G2;|fill234G@0|vdd_2|P
  35 Evdd_10||D5G2;|fill234G@0|vdd_3|P
  36 Evdd_11||D5G2;|fill234G@0|vdd_5|P
  37 X