chips/marina/electric/gates1inM.delib/invL30.sch

   1 Hgates1inM|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell invL30;1{sch}
   8 CinvL30;1{sch}||schematic|1223326987357|1223327401888|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-12|0|||XYRR|
  11 NOff-Page|conn@1||9.5|0|||XRR|
  12 IredFive:invLT;1{ic}|invLT@0||-1|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  13 Ngeneric:Invisible-Pin|pin@0||1|25|||||ART_message(D5G6;)SinvL30
  14 Ngeneric:Invisible-Pin|pin@1||1|20|||||ART_message(D5G4;)Slo threshold inverter
  15 Ngeneric:Invisible-Pin|pin@2||1|12|||||ART_message(D5G3;)Sies 6 October 2008
  16 Awire|net@0|||1800|conn@0|y|-10|0|invLT@0|in|-3.5|0
  17 Awire|net@1|||0|conn@1|a|7.5|0|invLT@0|out|1.5|0
  18 Ein||D4G2;|conn@0|a|I
  19 Eout||D6G2;|conn@1|y|O
  20 X