chips/marina/electric/gates2inM.delib/mux10:2.sch

   1 Hgates2inM|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell mux10/2;1{sch}
   8 Cmux10/2;1{sch}||schematic|1215934868816|1218475594813|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@1||-12|0||||
  11 NOff-Page|conn@2||12|0||||
  12 NOff-Page|conn@3||-8|-6||||
  13 Ngeneric:Invisible-Pin|pin@0||0.5|17.5|||||ART_message(D5G3;)Sies 11 August 2008
  14 Ngeneric:Invisible-Pin|pin@1||-0.5|21.5|||||ART_message(D5G4;)Stri-state selector = 1/2 mux
  15 Ngeneric:Invisible-Pin|pin@2||1.5|26.5|||||ART_message(D5G6;)Smux10/2
  16 NWire_Pin|pin@6||0|6||||
  17 NWire_Pin|pin@12||0|-6||||
  18 IredFive:triInv;1{ic}|triInv@0||0|0|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-1.5;)I100|ATTR_X(D5G1.5;NPX2.5;Y2;)S10
  19 Awire|net@3|||1800|conn@1|y|-10|0|triInv@0|in|-2.5|0
  20 Awire|net@10|||0|conn@2|a|10|0|triInv@0|out|2.5|0
  21 Awire|s[F]|D5G2;||2700|triInv@0|enB|0|2|pin@6||0|6
  22 Awire|s[T]|D5G2;||900|triInv@0|en|0|-2|pin@12||0|-6
  23 EinA[1]|in[1]|D4G2;|conn@1|a|I
  24 Eout[1]||D6G2;|conn@2|y|O
  25 Es[T,F]||D4G2;|conn@3|a|I
  26 X