chips/marina/electric/gates2inM.delib/mux10.sch

   1 Hgates2inM|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell mux10;1{sch}
   8 Cmux10;1{sch}||schematic|1215934868816|1218475251454|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-12|-9||||
  11 NOff-Page|conn@1||-12|9||||
  12 NOff-Page|conn@2||12|0||||
  13 NOff-Page|conn@3||-12|0||||
  14 Imux10;1{ic}|mux10@1||29|17|||D5G4;
  15 Ngeneric:Invisible-Pin|pin@0||0.5|23.5|||||ART_message(D5G3;)Sies 13 July 2008
  16 Ngeneric:Invisible-Pin|pin@1||-0.5|27.5|||||ART_message(D5G4;)Stwo input inverting mux
  17 Ngeneric:Invisible-Pin|pin@2||1.5|32.5|||||ART_message(D5G6;)Smux10
  18 NWire_Pin|pin@3||6|9||||
  19 NWire_Pin|pin@4||6|-9||||
  20 NWire_Pin|pin@5||6|0||||
  21 NWire_Pin|pin@6||0|15||||
  22 NWire_Pin|pin@9||0|-15||||
  23 IredFive:triInv;1{ic}|triInv@0||0|9|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-1.5;)I100|ATTR_X(D5G1.5;NPX2.5;Y2;)S10
  24 IredFive:triInv;1{ic}|triInv@1||0|-9|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-1.5;)I100|ATTR_X(D5G1.5;NPX2.5;Y2;)S10
  25 Awire|net@0|||1800|triInv@0|out|2.5|9|pin@3||6|9
  26 Awire|net@1|||900|pin@3||6|9|pin@5||6|0
  27 Awire|net@2|||0|pin@4||6|-9|triInv@1|out|2.5|-9
  28 Awire|net@3|||1800|conn@1|y|-10|9|triInv@0|in|-2.5|9
  29 Awire|net@4|||1800|conn@0|y|-10|-9|triInv@1|in|-2.5|-9
  30 Awire|net@5|||900|pin@5||6|0|pin@4||6|-9
  31 Awire|net@6|||0|conn@2|a|10|0|pin@5||6|0
  32 Awire|s[F]|D5G2;||2700|triInv@0|enB|0|11|pin@6||0|15
  33 Awire|s[F]|D5G2;||900|triInv@1|en|0|-11|pin@9||0|-15
  34 Awire|s[T]|D5G2;||2700|triInv@1|enB|0|-7|triInv@0|en|0|7
  35 EinA[1]||D4G2;|conn@1|a|I
  36 EinB[1]||D4G2;|conn@0|a|I
  37 Eout[1]||D6G2;|conn@2|y|O
  38 Es[T,F]||D4G2;|conn@3|a|I
  39 X