chips/marina/electric/gates2inM.delib/nand10symLT.sch

   1 Hgates2inM|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell nand10symLT;1{sch}
   8 Cnand10symLT;1{sch}||schematic|1189031371358|1234813117849|I
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||11|0||||
  11 NOff-Page|conn@1||-9.5|-1|||Y|
  12 NOff-Page|conn@2||-9.5|1|||Y|
  13 IredFive:nand2LT_sy;1{ic}|nand2LT_@0||-0.5|0|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.5;Y2.5;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  14 Ngeneric:Invisible-Pin|pin@0||0|12.5|||||ART_message(D5G5;)Snand10sym
  15 Ngeneric:Invisible-Pin|pin@1||0.5|8.5|||||ART_message(D5G3;)Sies 10 October 2007
  16 Awire|net@0|||1800|conn@1|y|-7.5|-1|nand2LT_@0|ina|-3|-1
  17 Awire|net@1|||1800|conn@2|y|-7.5|1|nand2LT_@0|inb|-3|1
  18 Awire|net@2|||1800|nand2LT_@0|out|2|0|conn@0|a|9|0
  19 EinA||D4G2;|conn@1|a|I
  20 EinB||D4G2;|conn@2|a|I
  21 Eout||D6G2;|conn@0|y|O
  22 X