chips/marina/electric/gates2inM.delib/nor05sym.sch

   1 Hgates2inM|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell nor05sym;1{sch}
   8 Cnor05sym;1{sch}||schematic|1189031371358|1226166277714|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||11|0||||
  11 NOff-Page|conn@1||-12.5|-3|||Y|
  12 NOff-Page|conn@2||-12.5|3|||Y|
  13 IredFive:nor2_sy;1{ic}|nor2n@1||0|0|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_LEGATE(T)I1|ATTR_LEPARALLGRP()I-1|ATTR_su(T)I-1
  14 Ngeneric:Invisible-Pin|pin@0||0|18.5|||||ART_message(D5G5;)Snor05sym
  15 Ngeneric:Invisible-Pin|pin@1||0.5|14.5|||||ART_message(D5G3;)Sies 4 October 2007
  16 NWire_Pin|pin@4||-7|-1||||
  17 NWire_Pin|pin@5||-7|-3||||
  18 NWire_Pin|pin@12||-7|3||||
  19 NWire_Pin|pin@13||-7|1||||
  20 Awire|net@8|||1800|conn@1|y|-10.5|-3|pin@5||-7|-3
  21 Awire|net@9|||900|pin@4||-7|-1|pin@5||-7|-3
  22 Awire|net@18|||0|nor2n@1|ina|-2.5|-1|pin@4||-7|-1
  23 Awire|net@22|||1800|nor2n@1|out|2.5|0|conn@0|a|9|0
  24 Awire|net@23|||1800|conn@2|y|-10.5|3|pin@12||-7|3
  25 Awire|net@24|||900|pin@12||-7|3|pin@13||-7|1
  26 Awire|net@25|||1800|pin@13||-7|1|nor2n@1|inb|-2.5|1
  27 EinA||D4G2;|conn@1|a|I
  28 EinB||D4G2;|conn@2|a|I
  29 Eout||D6G2;|conn@0|y|O
  30 X