chips/marina/electric/gates2inM.delib/nor10.sch

   1 Hgates2inM|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell nor10;1{sch}
   8 Cnor10;1{sch}||schematic|1189031371358|1234381255928|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||11|0||||
  11 NOff-Page|conn@1||-12.5|1.5|||Y|
  12 NOff-Page|conn@2||-12.5|-1.5|||Y|
  13 IredFive:nor2n;1{ic}|nor2n@1||0|0|Y||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  14 Ngeneric:Invisible-Pin|pin@0||0|18.5|||||ART_message(D5G5;)Snor10
  15 Ngeneric:Invisible-Pin|pin@1||0.5|14.5|||||ART_message(D5G3;)Sies 6 January 2008
  16 NWire_Pin|pin@4||-7|-1||||
  17 NWire_Pin|pin@6||6|0||||
  18 NWire_Pin|pin@8||6|0||||
  19 NWire_Pin|pin@13||-7|1||||
  20 NWire_Pin|pin@14||-7|1.5||||
  21 NWire_Pin|pin@15||-7|-1.5||||
  22 Awire|net@7|||0|nor2n@1|inb|-2.5|-1|pin@4||-7|-1
  23 Awire|net@10|||1800|nor2n@1|out|2.5|0|pin@6||6|0
  24 Awire|net@13|||900|pin@6||6|0|pin@8||6|0
  25 Awire|net@14|||0|conn@0|a|9|0|pin@8||6|0
  26 Awire|net@21|||1800|pin@13||-7|1|nor2n@1|ina|-2.5|1
  27 Awire|net@22|||900|pin@14||-7|1.5|pin@13||-7|1
  28 Awire|net@23|||1800|conn@1|y|-10.5|1.5|pin@14||-7|1.5
  29 Awire|net@24|||900|pin@4||-7|-1|pin@15||-7|-1.5
  30 Awire|net@25|||1800|conn@2|y|-10.5|-1.5|pin@15||-7|-1.5
  31 EinA||D4G2;|conn@1|a|I
  32 EinB||D4G2;|conn@2|a|I
  33 Eout||D6G2;|conn@0|y|O
  34 X