chips/marina/electric/gates2inM.delib/nor5.5sym.sch

   1 Hgates2inM|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell nor5.5sym;1{sch}
   8 Cnor5.5sym;1{sch}||schematic|1189031371358|1227396046435|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||12|0||||
  11 NOff-Page|conn@1||-12|-3|||Y|
  12 NOff-Page|conn@2||-12|3|||XYRR|
  13 IredFive:nor2_sy;1{ic}|nor2_sy@2||0|0|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.25;Y2.25;)S5.5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  14 Inor5.5sym;2{ic}|nor3in3.@1||17|7.5|||D5G4;
  15 Ngeneric:Invisible-Pin|pin@0||0|18.5|||||ART_message(D5G5;)Snor5.5sym
  16 Ngeneric:Invisible-Pin|pin@1||0.5|14.5|||||ART_message(D5G3;)Sies 12 April 2008
  17 NWire_Pin|pin@26||-6|3||||
  18 NWire_Pin|pin@28||-6|1||||
  19 NWire_Pin|pin@29||-6|-3||||
  20 NWire_Pin|pin@31||-6|-1||||
  21 Awire|net@62|||1800|conn@2|y|-10|3|pin@26||-6|3
  22 Awire|net@65|||1800|pin@28||-6|1|nor2_sy@2|inb|-2.5|1
  23 Awire|net@66|||1800|conn@1|y|-10|-3|pin@29||-6|-3
  24 Awire|net@69|||1800|pin@31||-6|-1|nor2_sy@2|ina|-2.5|-1
  25 Awire|net@70|||0|conn@0|a|10|0|nor2_sy@2|out|2.5|0
  26 Awire|net@71|||900|pin@26||-6|3|pin@28||-6|1
  27 Awire|net@72|||2700|pin@29||-6|-3|pin@31||-6|-1
  28 EinA||D4G2;|conn@1|a|I
  29 EinB||D4G2;|conn@2|a|I
  30 Eout||D6G2;|conn@0|y|O
  31 X