chips/marina/electric/gates2inM.delib/xorAmp20.sch

   1 Hgates2inM|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LredFive|redFive
   8
   9 # Cell xorAmp20;1{sch}
  10 CxorAmp20;1{sch}||schematic|1189031371358|1205536772914|
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||18|0||||
  13 NOff-Page|conn@1||-30|-0.5||||
  14 NOff-Page|conn@3||-30|6|||Y|
  15 IredFive:inv;1{ic}|inv@0||-21|3|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  16 IredFive:inv;1{ic}|inv@1||12|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  17 IredFive:inv;1{ic}|inv@2||-21|-3.5|Y||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  18 Ngeneric:Invisible-Pin|pin@0||-4|25|||||ART_message(D5G5;)SxorAmp20
  19 Ngeneric:Invisible-Pin|pin@1||-3.5|21|||||ART_message(D5G3;)Sies 1 January 2008
  20 NWire_Pin|pin@30||-9|0.5||||
  21 NWire_Pin|pin@31||-9|3||||
  22 NWire_Pin|pin@39||-6|1.5||||
  23 NWire_Pin|pin@40||-6|6||||
  24 NWire_Pin|pin@42||-26|6||||
  25 NWire_Pin|pin@43||-26|3||||
  26 Ngeneric:Invisible-Pin|pin@48||-4|18|||||ART_message(D5G2;)Sboth inputs true gives false output
  27 Ngeneric:Invisible-Pin|pin@49||-4|15.5|||||ART_message(D5G2;)Strue B inverts A
  28 NWire_Pin|pin@50||-9|-3.5||||
  29 NWire_Pin|pin@51||-9|-1.5||||
  30 NWire_Pin|pin@55||-26|-3.5||||
  31 NWire_Pin|pin@56||-26|-0.5||||
  32 IorangeTSMC090nm:wire90;1{ic}|wire90@0||-13.5|3|||D0G4;|ATTR_L(D5G1;PUD)D268.40000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)S1|ATTR_width(D5G1;NPY-2;)I3
  33 IorangeTSMC090nm:wire90;1{ic}|wire90@1||6|0|||D0G4;|ATTR_L(D5G1;PUD)D332.4|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)S1|ATTR_width(D5G1;NPY-2;)I3
  34 IorangeTSMC090nm:wire90;1{ic}|wire90@2||-13.5|-3.5|||D0G4;|ATTR_L(D5G1;PUD)D231.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)S1|ATTR_width(D5G1;NPY-2;)I3
  35 IredFive:xor2;1{ic}|xor2@0||0|0|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  36 IxorAmp20;1{ic}|xor10@0||6.5|10.5|||D5G4;
  37 Awire|net@50|||1800|pin@30||-9|0.5|xor2@0|inbB|-3.5|0.5
  38 Awire|net@56|||2700|pin@30||-9|0.5|pin@31||-9|3
  39 Awire|net@61|||1800|inv@0|out|-18.5|3|wire90@0|a|-16|3
  40 Awire|net@62|||1800|wire90@0|b|-11|3|pin@31||-9|3
  41 Awire|net@71|||0|xor2@0|inb|-3.5|1.5|pin@39||-6|1.5
  42 Awire|net@72|||2700|pin@39||-6|1.5|pin@40||-6|6
  43 Awire|net@75|||0|pin@40||-6|6|pin@42||-26|6
  44 Awire|net@76|||0|pin@42||-26|6|conn@3|y|-28|6
  45 Awire|net@77|||900|pin@42||-26|6|pin@43||-26|3
  46 Awire|net@78|||1800|pin@43||-26|3|inv@0|in|-23.5|3
  47 Awire|net@83|||1800|xor2@0|out|1.5|0|wire90@1|a|3.5|0
  48 Awire|net@84|||1800|wire90@1|b|8.5|0|inv@1|in|9.5|0
  49 Awire|net@85|||1800|inv@1|out|14.5|0|conn@0|a|16|0
  50 Awire|net@90|||1800|inv@2|out|-18.5|-3.5|wire90@2|a|-16|-3.5
  51 Awire|net@92|||0|pin@50||-9|-3.5|wire90@2|b|-11|-3.5
  52 Awire|net@93|||900|pin@51||-9|-1.5|pin@50||-9|-3.5
  53 Awire|net@100|||0|inv@2|in|-23.5|-3.5|pin@55||-26|-3.5
  54 Awire|net@101|||1800|conn@1|y|-28|-0.5|pin@56||-26|-0.5
  55 Awire|net@102|||2700|pin@55||-26|-3.5|pin@56||-26|-0.5
  56 Awire|net@103|||0|xor2@0|inaB|-3.5|-1.5|pin@51||-9|-1.5
  57 Awire|net@105|||1800|pin@56||-26|-0.5|xor2@0|ina|-3.5|-0.5
  58 EinA[T,F]|inA[1]|D4G2;|conn@1|a|I
  59 EinB[T,F]|inB[1]|D4G2;|conn@3|a|I
  60 Eout|out[1]|D6G2;|conn@0|y|O
  61 X