chips/marina/electric/gates3inM.delib/nand3in6.6.sch

   1 Hgates3inM|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell nand3in6.6;1{sch}
   8 Cnand3in6.6;1{sch}||schematic|1189031371358|1240579595297|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||11|0||||
  11 NOff-Page|conn@1||-9.5|-2|||Y|
  12 NOff-Page|conn@2||-9.5|0|||Y|
  13 NOff-Page|conn@3||-9.5|2|||Y|
  14 IredFive:nand3;1{ic}|nand3@0||0|0|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5G1.5;NPX3;Y2.5;)S6.667|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  15 Ngeneric:Invisible-Pin|pin@0||0|12.5|||||ART_message(D5G5;)Snand3in6.6
  16 Ngeneric:Invisible-Pin|pin@1||0.5|8.5|||||ART_message(D5G3;)Sies 5 October 2007
  17 Awire|net@5|||0|conn@0|a|9|0|nand3@0|out|2.5|0
  18 Awire|net@11|||1800|conn@1|y|-7.5|-2|nand3@0|ina|-2.5|-2
  19 Awire|net@12|||1800|conn@2|y|-7.5|0|nand3@0|inb|-2.5|0
  20 Awire|net@13|||1800|conn@3|y|-7.5|2|nand3@0|inc|-2.5|2
  21 EinA||D4G2;|conn@1|a|I
  22 EinB||D4G2;|conn@2|a|I
  23 EinC||D4G2;|conn@3|a|I
  24 Eout||D6G2;|conn@0|y|O
  25 X