chips/marina/electric/jtagController.delib/clockGen.ic

   1 HjtagController|8.10k
   2
   3 # Cell clockGen;1{ic}
   4 CclockGen;1{ic}||artwork|1028674092000|1185367908213|EI|FACET_schematic_page_size()Sh|USER_drawing_designer_name()Sivans|prototype_center()I[0,0]
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 NOpened-Thicker-Polygon|art@1||0|0|6|10|||trace()V[-3/-5,-3/5,3/5,3/-5,-3/-5]
   7 Ngeneric:Invisible-Pin|pin@0||0|-4.5|||||ART_message(D5G1;)S[fb2]
   8 Ngeneric:Invisible-Pin|pin@1||0|4.25|||||ART_message(D5G1;)S[fb1]
   9 Nschematic:Wire_Pin|pin@2||0|7|||YRRR|
  10 Ngeneric:Invisible-Pin|pin@3||0|5|||RRR|
  11 Nschematic:Wire_Pin|pin@4||0|-7|||RRR|
  12 Ngeneric:Invisible-Pin|pin@5||0|-5|||RRR|
  13 Ngeneric:Invisible-Pin|pin@6||-2|0|||||ART_message(D5G1;)S[clk]
  14 Ngeneric:Invisible-Pin|pin@7||1.75|-3|||||ART_message(D5G1;)S[phi2]
  15 Ngeneric:Invisible-Pin|pin@8||1.75|3|||||ART_message(D5G1;)S[phi1]
  16 Nschematic:Wire_Pin|pin@9||3|-3|||YRR|
  17 Ngeneric:Invisible-Pin|pin@10||5|-3|||RR|
  18 Nschematic:Wire_Pin|pin@11||3|3|||YRR|
  19 Ngeneric:Invisible-Pin|pin@12||5|3|||RR|
  20 Nschematic:Wire_Pin|pin@13||-3|0||||
  21 Ngeneric:Invisible-Pin|pin@14||-5|0||||
  22 Aschematic:wire|net@0|||900|pin@2||0|7|pin@3||0|5
  23 Aschematic:wire|net@1|||2700|pin@4||0|-7|pin@5||0|-5
  24 Aschematic:wire|net@2|||1800|pin@9||3|-3|pin@10||5|-3
  25 Aschematic:wire|net@3|||1800|pin@11||3|3|pin@12||5|3
  26 Aschematic:wire|net@4|||0|pin@13||-3|0|pin@14||-5|0
  27 Eclk||D5G2;|pin@14||I
  28 Ephi1_fb||D5G2;|pin@2||I
  29 Ephi1_out||D5G2;|pin@12||O
  30 Ephi2_fb||D5G2;|pin@4||I
  31 Ephi2_out||D5G2;|pin@10||O
  32 X