chips/marina/electric/jtagController.delib/slaveBit.sch

   1 HjtagController|8.10k
   2
   3 # External Libraries:
   4
   5 LjtagScan|jtagScan
   6
   7 LorangeTSMC090nm|orangeTSMC090nm
   8
   9 LredFive|redFive
  10
  11 # Cell slaveBit;1{sch}
  12 CslaveBit;1{sch}||schematic|1031347345000|1187020003237|I
  13 NOff-Page|conn@0||20|-24|||RRR|
  14 NOff-Page|conn@1||-6.5|0||||
  15 NOff-Page|conn@2||6|9|||RRR|
  16 IredFive:inv;1{ic}|inv@0||20|-7|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)F3.3|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  17 Ngeneric:Invisible-Pin|pin@2||-10|16|||||ART_message(D5G2;)S[slave-only state-holding bit (for TMS)]
  18 Ngeneric:Invisible-Pin|pin@3||-8|19.5|||||ART_message(D5G5;)S[slaveBit]
  19 NWire_Pin|pin@4||20|0||||
  20 IjtagScan:scan_write;1{ic}|scan_wri@0||9|0|||D5G4;
  21 IslaveBit;1{ic}|slaveBit@0||18|11|||D0G4;
  22 IorangeTSMC090nm:wire90;1{ic}|wire180@0||20|-16.25|RRR||D0G4;|ATTR_L(D5G1;PUD)I500|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  23 Awire|net@8|||2700|inv@0|in|20|-4.5|pin@4||20|0
  24 Awire|net@11|||1800|scan_wri@0|dout|15|0|pin@4||20|0
  25 Awire|net@12|||0|scan_wri@0|din|4|0|conn@1|y|-4.5|0
  26 Awire|net@13|||900|conn@2|y|6|7|scan_wri@0|wr|6|2
  27 Awire|net@20|||900|wire180@0|b|20|-18.75|conn@0|a|20|-22
  28 Awire|net@21|||900|inv@0|out|20|-9.5|wire180@0|a|20|-13.75
  29 Edin||D5G2;|conn@1|y|I
  30 Ephi2||D5G2;|conn@2|y|I
  31 Eslave||D5G2;|conn@0|y|O
  32 X