chips/marina/electric/jtagScan.delib/passT.sch

   1 HjtagScan|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell passT;1{sch}
   8 CpassT;1{sch}||schematic|1071172825000|1185367908213|I|FACET_schematic_page_size()Sh|USER_drawing_designer_name()Sivans|prototype_center()I[0,0]
   9 IredFive:NMOS;1{ic}|NMOS@0||-5|3|RRR||D0G4;|ATTR_Delay(D5G1;NOJPX-0.5;Y-4;)S100|ATTR_X(D5G1;NPX-1.5;Y-3.5;)S10
  10 IredFive:PMOS;1{ic}|PMOS@0||-5|3|R||D0G4;|ATTR_Delay(D5G1;NOJPX-0.5;Y4;)S100|ATTR_X(D5G1;NPX-1.5;Y3.5;)S5
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||-5|18.5|||YR|
  13 NOff-Page|conn@1||-14|3|||Y|
  14 NOff-Page|conn@2||7|3||||
  15 IredFive:inv;1{ic}|inv@0||0|8|XRRR||D5G4;|ATTR_Delay(D5G1;NPX2;Y-2;)S0|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S11/3.|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  16 Ngeneric:Invisible-Pin|pin@4||-4|26.5|||||ART_message(D5G2;)Sthe scanner pass gate - gets only T control intput
  17 Ngeneric:Invisible-Pin|pin@5||-4|30.5|||||ART_message(D5G6;)SpassT
  18 NWire_Pin|pin@52||0|13||||
  19 NWire_Pin|pin@53||-5|13||||
  20 NWire_Pin|pin@54||0|-3||||
  21 NWire_Pin|pin@55||-5|-3||||
  22 IpassT;1{ic}|scanP@0||13|19|||D0G4;
  23 Awire|net@84|||900|pin@53||-5|13|NMOS@0|g|-5|6
  24 Awire|net@85|||2700|inv@0|in|0|10.5|pin@52||0|13
  25 Awire|net@86|||900|conn@0|y|-5|16.5|pin@53||-5|13
  26 Awire|net@87|||0|pin@52||0|13|pin@53||-5|13
  27 Awire|net@88|||900|inv@0|out|0|5.5|pin@54||0|-3
  28 Awire|net@89|||0|pin@54||0|-3|pin@55||-5|-3
  29 Awire|net@90|||2700|pin@55||-5|-3|PMOS@0|g|-5|0
  30 Awire|net@91|||1800|conn@1|y|-12|3|NMOS@0|s|-7|3
  31 Awire|net@92|||900|PMOS@0|s|-7|3|NMOS@0|s|-7|3
  32 Awire|net@93|||1800|PMOS@0|d|-3|3|conn@2|a|5|3
  33 Awire|net@94|||900|NMOS@0|d|-3|3|PMOS@0|d|-3|3
  34 Edrn||D5G2;|conn@2|y|O
  35 EpassT||D5G2;|conn@0|a|I
  36 Esrc||D5G2;|conn@1|a|I
  37 X