chips/marina/electric/jtagScan.delib/scanCL.sch

   1 HjtagScan|8.10k
   2
   3 # Cell scanCL;1{sch}
   4 CscanCL;1{sch}||schematic|1071024267000|1185367908213|I|FACET_schematic_page_size()Sh|USER_drawing_designer_name()Sivans|prototype_center()I[0,0]
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 NOff-Page|conn@1||9|18|||RRR|
   7 NOff-Page|conn@4||-42.5|-23||||
   8 NOff-Page|conn@5||18.5|-23||||
   9 NGround|gnd@1||21.5|9|||R|
  10 Ngeneric:Invisible-Pin|pin@13||-5|-19|||||ART_message(D5G2;)Sscan write, unused here
  11 Ngeneric:Invisible-Pin|pin@14||-5|27.5|||||ART_message(D5G2;)Sit sets con[0] to LO on Master Clear
  12 Ngeneric:Invisible-Pin|pin@15||-7|34.5|||||ART_message(D5G6;)S[scanCL]
  13 Ngeneric:Invisible-Pin|pin@16||-5|30.5|||||ART_message(D5G2;)S["scanCL serves as a keeper for \"con[0]\""]
  14 NBus_Pin|pin@22||-18|-1||||
  15 NBus_Pin|pin@23||-5|-1||||
  16 NWire_Pin|pin@25||5|-10||||
  17 NBus_Pin|pin@26||5|-1||||
  18 NWire_Pin|pin@27||0|9||||
  19 NBus_Pin|pin@30||15|-1||||
  20 NBus_Pin|pin@31||-32.5|-23|-1|-1||
  21 NBus_Pin|pin@32||-32.5|-30|-1|-1||
  22 NBus_Pin|pin@33||-19.5|-23|-1|-1||
  23 NBus_Pin|pin@34||-14.5|-23|-1|-1||
  24 NWire_Pin|pin@35||19|-14||||
  25 NWire_Pin|pin@37||-32|-14||||
  26 NBus_Pin|pin@39||-44.5|-1||||
  27 IscanCL;1{ic}|scanCL@0||41|35|||D0G4;
  28 Iscan_shift;1{ic}|scan_shi@0||-5|-14|||D5G4;
  29 Iscan_write_sizeable;1{ic}|scan_wri@0||12|9|XY||D5G4;
  30 Awire|mc|D5G2;||900|scan_wri@0|wr|15|7|pin@30||15|-1
  31 Abus|net@33||-0.5|IJ1800|pin@22||-18|-1|pin@23||-5|-1
  32 Abus|net@35||-0.5|IJ1800|pin@23||-5|-1|pin@26||5|-1
  33 Awire|net@38|||1800|scan_shi@0|rd|2|-10|pin@25||5|-10
  34 Awire|net@43|||2700|scan_shi@0|rddata|0|-8|pin@27||0|9
  35 Awire|net@49|||0|gnd@1||19.5|9|scan_wri@0|din|17|9
  36 Awire|net@51|||0|scan_wri@0|dout|6|9|pin@27||0|9
  37 Awire|net@52|||900|conn@1|y|9|16|scan_wri@0|kept|9|12
  38 Abus|net@54||-0.5|IJ1800|pin@26||5|-1|pin@30||15|-1
  39 Abus|net@55||-0.5|IJ1800|conn@4|y|-40.5|-23|pin@31||-32.5|-23
  40 Abus|net@56||-0.5|IJ1800|pin@31||-32.5|-23|pin@33||-19.5|-23
  41 Awire|phi1|D5G2;||2700|scan_shi@0|phi1|-5|-12|pin@23||-5|-1
  42 Awire|phi2|D5G2;||2700|scan_shi@0|phi2|-18|-12|pin@22||-18|-1
  43 Abus|phi2,phi1,rd,mclr|D8G2;Y0.25;|-0.5|IJ1800|pin@39||-44.5|-1|pin@22||-18|-1|ART_color()I0
  44 Awire|rd|D5G2;||2700|pin@25||5|-10|pin@26||5|-1
  45 Awire|sin|D8G2;||1800|pin@37||-32|-14|scan_shi@0|sdin|-20|-14|ART_color()I0
  46 Abus|sin,phi2,phi1,wr,rd,phi1_return,phi2_return,scan_data_return,mc|D5G2;|-0.5|IJ900|pin@31||-32.5|-23|pin@32||-32.5|-30
  47 Awire|sout|D8G2;||0|pin@35||19|-14|scan_shi@0|sdout|9|-14|ART_color()I0
  48 Abus|sout,jtagIn[2:8],mc|D8G2;Y0.25;|-0.5|IJ0|conn@5|a|16.5|-23|pin@34||-14.5|-23
  49 Econ[0]||D5G2;X-1;|conn@1|a|B
  50 EjtagIn[8:0]|jtagIn[1:9]|D5G2;|conn@4|a|B
  51 EjtagOut[8:0]|jtagOut[1:9]|D5G2;|conn@5|y|B
  52 X