chips/marina/electric/jtagScan.delib/scanIRL.sch

   1 HjtagScan|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell scanIRL;1{sch}
   8 CscanIRL;1{sch}||schematic|992379436000|1185367908213|I|FACET_schematic_page_size()Sh|USER_drawing_designer_name()Sivans|prototype_center()I[0,0]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@2||-2|23|||R|
  11 NOff-Page|conn@4||4|23|||R|
  12 NOff-Page|conn@7||-50|-28||||
  13 NOff-Page|conn@8||11|-28||||
  14 IredFive:inv;1{ic}|invLT@1||-2|13.5|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S7.2|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  15 Ngeneric:Invisible-Pin|pin@10||-10.4|32.02|||||ART_message(D5G2;)S["it can write or reset its output to HI,  and always reads a LO"]
  16 Ngeneric:Invisible-Pin|pin@11||-12.4|39.02|||||ART_message(D5G6;)S[scanIRL]
  17 Ngeneric:Invisible-Pin|pin@12||-10.4|35.02|||||ART_message(D5G2;)S[used to implement the JTAG instruction register]
  18 NWire_Pin|pin@17||-2|9||||
  19 NWire_Pin|pin@18||4|9||||
  20 NBus_Pin|pin@19||-19|-3||||
  21 NWire_Pin|pin@20||4|-13||||
  22 NBus_Pin|pin@21||4|-3||||
  23 NWire_Pin|pin@22||27|9||||
  24 NWire_Pin|pin@23||27|-17||||
  25 NBus_Pin|pin@24||21|-3||||
  26 NWire_Pin|pin@25||11|5||||
  27 NBus_Pin|pin@26||11|-3||||
  28 NBus_Pin|pin@27||-6|-3||||
  29 NBus_Pin|pin@28||-38|-3||||
  30 NBus_Pin|pin@29||-40|-28|-1|-1||
  31 NBus_Pin|pin@30||-40|-35|-1|-1||
  32 NBus_Pin|pin@31||-27|-28|-1|-1||
  33 NBus_Pin|pin@32||-22|-28|-1|-1||
  34 NWire_Pin|pin@33||-43|-17||||
  35 NPower|pwr@2||16|0||||
  36 NPower|pwr@3||-1|-6||||
  37 IscanIRL;1{ic}|scanIRL@0||40|21.5|||D0G4;
  38 Iscan_shift;1{ic}|scan_shi@0||-6|-17|||D5G4;
  39 Iscan_write_mc;1{ic}|scan_wri@0||16|9|XY||D5G4;
  40 Awire|mc|D5G2;||900|pin@25||11|5|pin@26||11|-3
  41 Awire|net@28|||2700|pin@17||-2|9|invLT@1|in|-2|11
  42 Abus|net@29||-0.5|IJ0|pin@27||-6|-3|pin@19||-19|-3
  43 Abus|net@30||-0.5|IJ0|pin@24||21|-3|pin@26||11|-3
  44 Awire|net@31|||0|scan_wri@0|mc|14|5|pin@25||11|5
  45 Abus|net@32||-0.5|IJ0|pin@26||11|-3|pin@21||4|-3
  46 Awire|net@33|||2700|pwr@2||16|0|scan_wri@0|mcdata|16|3
  47 Awire|net@34|||1800|pin@17||-2|9|pin@18||4|9
  48 Awire|net@36|||1800|scan_shi@0|rd|1|-13|pin@20||4|-13
  49 Abus|net@37||-0.5|IJ0|pin@21||4|-3|pin@27||-6|-3
  50 Awire|net@38|||0|scan_wri@0|dout|8|9|pin@18||4|9
  51 Awire|net@39|||1800|scan_wri@0|wrdata|23|9|pin@22||27|9
  52 Awire|net@41|||900|pin@22||27|9|pin@23||27|-17
  53 Awire|net@42|||900|conn@2|a|-2|21|invLT@1|out|-2|16
  54 Awire|net@43|||900|conn@4|a|4|21|pin@18||4|9
  55 Awire|net@47|||900|pwr@3||-1|-6|scan_shi@0|rddata|-1|-11
  56 Abus|net@51||-0.5|IJ1800|conn@7|y|-48|-28|pin@29||-40|-28
  57 Abus|net@52||-0.5|IJ1800|pin@29||-40|-28|pin@31||-27|-28
  58 Awire|phi1|D5G2;||900|pin@27||-6|-3|scan_shi@0|phi1|-6|-15
  59 Awire|phi2|D5G2;||900|pin@19||-19|-3|scan_shi@0|phi2|-19|-15
  60 Abus|phi2,phi1,wr,rd,mc|D8G2;Y0.25;|-0.5|IJ1800|pin@28||-38|-3|pin@19||-19|-3
  61 Awire|rd|D5G2;||2700|pin@20||4|-13|pin@21||4|-3
  62 Awire|sin|D8G2;||0|scan_shi@0|sdin|-21|-17|pin@33||-43|-17
  63 Abus|sin,phi2,phi1,wr,rd,phi1_return,phi2_return,scan_data_return,mc|D5G2;|-0.5|IJ900|pin@29||-40|-28|pin@30||-40|-35
  64 Awire|sout|D8G2;||0|pin@23||27|-17|scan_shi@0|sdout|8|-17
  65 Abus|sout,jtagIn[2:8],mc|D8G2;Y0.25;|-0.5|IJ0|conn@8|a|9|-28|pin@32||-22|-28
  66 Awire|wr|D5G2;||900|scan_wri@0|wr|21|7|pin@24||21|-3
  67 Edout||D5G2;|conn@2|y|O
  68 Edoutb||D5G2;|conn@4|y|O
  69 EjtagIn[8:0]|jtagIn[1:9]|D5G2;|conn@7|a|B
  70 EjtagOut[8:0]|jtagOut[1:9]|D5G2;|conn@8|y|B
  71 X