chips/marina/electric/jtagScan.delib/scanRL.sch

   1 HjtagScan|8.10k
   2
   3 # Cell scanRL;1{sch}
   4 CscanRL;1{sch}||schematic|992379436000|1185367908213|I|FACET_schematic_page_size()Sh|USER_drawing_designer_name()Sivans|prototype_center()I[0,0]
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 NOff-Page|conn@3||-31|-21||||
   7 NOff-Page|conn@4||30|-21||||
   8 Ngeneric:Invisible-Pin|pin@1||-14|26|||||ART_message(D5G2;)S["scanRL implements the JTAG \"Bypass\" Register"]
   9 Ngeneric:Invisible-Pin|pin@2||-16|30|||||ART_message(D5G6;)S[scanRL]
  10 Ngeneric:Invisible-Pin|pin@3||-14|23|||||ART_message(D5G2;)S[it will always set its output to a logic LO on a read]
  11 NBus_Pin|pin@8||-12|4||||
  12 NWire_Pin|pin@9||11|-6||||
  13 NBus_Pin|pin@10||11|4||||
  14 NBus_Pin|pin@11||1|4||||
  15 NBus_Pin|pin@12||-21|-21|-1|-1||
  16 NBus_Pin|pin@13||-21|-28|-1|-1||
  17 NBus_Pin|pin@14||-8|-21|-1|-1||
  18 NBus_Pin|pin@15||-3|-21|-1|-1||
  19 NWire_Pin|pin@16||-20|-10||||
  20 NWire_Pin|pin@17||27|-10||||
  21 NBus_Pin|pin@18||-24|4|-1|-1||
  22 NPower|pwr@1||6|1||||
  23 IscanRL;1{ic}|scanRL@0||23|14.5|||D0G4;
  24 Iscan_shift;1{ic}|scan_shi@0||1|-10|||D5G4;
  25 Abus|net@11||-0.5|IJ0|pin@11||1|4|pin@8||-12|4
  26 Awire|net@12|||1800|scan_shi@0|rd|8|-6|pin@9||11|-6
  27 Abus|net@13||-0.5|IJ0|pin@10||11|4|pin@11||1|4
  28 Awire|net@14|||900|pwr@1||6|1|scan_shi@0|rddata|6|-4
  29 Abus|net@20||-0.5|IJ1800|conn@3|y|-29|-21|pin@12||-21|-21
  30 Abus|net@21||-0.5|IJ1800|pin@12||-21|-21|pin@14||-8|-21
  31 Awire|phi1|D5G2;||900|pin@11||1|4|scan_shi@0|phi1|1|-8
  32 Awire|phi2|D5G2;||900|pin@8||-12|4|scan_shi@0|phi2|-12|-8
  33 Abus|phi2,phi1,rd|D8G2;Y0.25;|-0.5|IJ1800|pin@18||-24|4|pin@8||-12|4
  34 Awire|rd|D5G2;||2700|pin@9||11|-6|pin@10||11|4
  35 Awire|sin|D8G2;||0|scan_shi@0|sdin|-14|-10|pin@16||-20|-10
  36 Abus|sin,phi2,phi1,wr,rd,phi1_return,phi2_return,scan_data_return,mc|D5G2;|-0.5|IJ900|pin@12||-21|-21|pin@13||-21|-28
  37 Awire|sout|D8G2;||1800|scan_shi@0|sdout|15|-10|pin@17||27|-10
  38 Abus|sout,jtagIn[2:8],mc|D8G2;Y0.25;|-0.5|IJ0|conn@4|a|28|-21|pin@15||-3|-21
  39 EjtagIn[8:0]|jtagIn[1:9]|D5G2;|conn@3|a|B
  40 EjtagOut[8:0]|jtagOut[1:9]|D5G2;|conn@4|y|B
  41 X