chips/marina/electric/latchGroupsK.delib/data1in10Bx2.sch

   1 HlatchGroupsK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 # Cell data1in10Bx2;1{sch}
   8 Cdata1in10Bx2;1{sch}||schematic|1194187081843|1209416691660|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-11.5|0||||
  11 NOff-Page|conn@1||-9.5|-6||||
  12 NOff-Page|conn@4||11.5|0||||
  13 IlatchesK:latch1in10B;1{ic}|lat[1:2]|D5G3;X4;Y4.5;|0|0|||D5G4;
  14 Ngeneric:Invisible-Pin|pin@0||-0.5|15.5|||||ART_message(D5G3;)Sies 28 April 2008
  15 Ngeneric:Invisible-Pin|pin@1||-1.5|19.5|||||ART_message(D5G4;)Stwo one input latch with two amplifiers
  16 Ngeneric:Invisible-Pin|pin@2||0.5|24.5|||||ART_message(D5G6;)Sdata1in10Bx2
  17 NWire_Pin|pin@33||-2|-6||||
  18 Abus|net@103||-0.5|IJ0|conn@4|a|9.5|0|lat[1:2]|out[1]|3|0
  19 Abus|net@107||-0.5|IJ1800|conn@0|y|-9.5|0|lat[1:2]|in[1]|-3|0
  20 Awire|net@110|||1800|conn@1|y|-7.5|-6|pin@33||-2|-6
  21 Awire|net@111|||2700|pin@33||-2|-6|lat[1:2]|hcl|-2|-3
  22 Ehcl||D4G2;|conn@1|a|I
  23 Ein[1:2]||D4G2;|conn@0|a|I
  24 Eout[1:2]||D6G2;|conn@4|y|O
  25 X