chips/marina/electric/latchGroupsK.delib/data1inTwin30.sch

   1 HlatchGroupsK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 # Cell data1inTwin30;1{sch}
   8 Cdata1inTwin30;1{sch}||schematic|1194187081843|1225976648446|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-21|-6||||
  11 NOff-Page|conn@1||-21|0||||
  12 NOff-Page|conn@4||5|0||||
  13 IlatchesK:latch1in30A;1{ic}|latch1in@0||-8|6|||D5G4;
  14 IlatchesK:latch1in30A;1{ic}|latch1in@1||-8|-6|Y||D5G4;
  15 Ngeneric:Invisible-Pin|pin@0||-0.5|21.5|||||ART_message(D5G3;)Sies 7 December 2007
  16 Ngeneric:Invisible-Pin|pin@1||-1.5|25.5|||||ART_message(D5G4;)Stwin latch with one amplifier
  17 Ngeneric:Invisible-Pin|pin@2||0.5|30.5|||||ART_message(D5G6;)Sdata1inTwin30
  18 NWire_Pin|pin@8||-10|0||||
  19 NWire_Pin|pin@9||-15|-6||||
  20 NWire_Pin|pin@10||-15|-11||||
  21 NWire_Pin|pin@11||-15|6||||
  22 NWire_Pin|pin@12||-15|11||||
  23 NWire_Pin|pin@15||0|-6||||
  24 NWire_Pin|pin@16||0|-11||||
  25 NWire_Pin|pin@17||0|11||||
  26 NWire_Pin|pin@18||0|6||||
  27 Ngeneric:Invisible-Pin|pin@19||-0.5|17.5|||||ART_message(D5G3;)Sm2 layout: ies 6 Nov 08
  28 Awire|in[1]|D5G2;||900|pin@9||-15|-6|pin@10||-15|-11
  29 Awire|in[2]|D5G2;||900|pin@12||-15|11|pin@11||-15|6
  30 Awire|net@8|||1800|conn@1|y|-19|0|pin@8||-10|0
  31 Awire|net@72|||1800|pin@11||-15|6|latch1in@0|in[1]|-11|6
  32 Awire|net@74|||0|latch1in@1|in[1]|-11|-6|pin@9||-15|-6
  33 Awire|net@77|||2700|pin@8||-10|0|latch1in@0|hcl|-10|3
  34 Awire|net@78|||900|pin@8||-10|0|latch1in@1|hcl|-10|-3
  35 Awire|net@81|||0|pin@18||0|6|latch1in@0|out[1]|-5|6
  36 Awire|net@82|||0|pin@15||0|-6|latch1in@1|out[1]|-5|-6
  37 Awire|out[1]|D5G2;||900|pin@15||0|-6|pin@16||0|-11
  38 Awire|out[2]|D5G2;||900|pin@17||0|11|pin@18||0|6
  39 Ehcl||D4G2;|conn@1|a|I
  40 Ein[1,2]||D4G2;|conn@0|a|I
  41 Eout[1,2]||D6G2;|conn@4|y|O
  42 X