chips/marina/electric/latchGroupsK.delib/data1inTwin30m1.lay

   1 HlatchGroupsK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 # Cell data1inTwin30m1;1{lay}
   8 Cdata1inTwin30m1;1{lay}|data1inTwin30|cmos90|1197076555516|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/",exportsConnectedByParent hcl hcl_1]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 IlatchesK:latch1in30Am1;1{lay}|latch1in@0||0|0|||D5G4;
  11 IlatchesK:latch1in30Am1w;1{lay}|latch1in@1||0|0|||D5G4;
  12 Ametal-2|net@85|||S0|latch1in@1|gnd_2|-4.4|0|latch1in@0|gnd_1|-4.4|0
  13 Ametal-2|net@86|||S0|latch1in@1|vdd_1|-4.4|-50|latch1in@0|vdd_1|-4.4|-50
  14 Ametal-2|net@87|||S0|latch1in@1|vdd_5|-4.4|50|latch1in@0|vdd_3|-4.4|50
  15 Egnd||D5G2;|latch1in@0|gnd|G
  16 Egnd_1||D5G2;|latch1in@1|gnd|G
  17 Ehcl||D5G2;|latch1in@0|hcl|I
  18 Ehcl_1||D5G2;|latch1in@1|hcl|I
  19 Ein[1]||D5G2;|latch1in@0|in[1]|I
  20 Ein[2]||D5G2;|latch1in@1|in[1]|I
  21 Eout[1]||D5G2;|latch1in@0|out[1]|O
  22 Eout[2]||D5G2;|latch1in@1|out[1]|O
  23 Evdd||D5G2;|latch1in@0|vdd|P
  24 Evdd_2||D5G2;|latch1in@0|vdd_2|P
  25 Evdd_3||D5G2;|latch1in@1|vdd|P
  26 Evdd_4||D5G2;|latch1in@1|vdd_3|P
  27 X