chips/marina/electric/latchGroupsK.delib/data2inTwin10A.sch

   1 HlatchGroupsK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 # Cell data2inTwin10A;1{sch}
   8 Cdata2inTwin10A;1{sch}||schematic|1194187081843|1207322512691|
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-11.5|-2||||
  11 NOff-Page|conn@1||-9.5|-6||||
  12 NOff-Page|conn@4||11.5|0||||
  13 NOff-Page|conn@5||-12|2||||
  14 NOff-Page|conn@6||-9|6||||
  15 IlatchesK:latch2in10A;1{ic}|lat[1:2]|D5G3;X4;Y4.5;|0|0|||D5G4;
  16 Ngeneric:Invisible-Pin|pin@0||-0.5|15.5|||||ART_message(D5G3;)Sies 4 March 2008
  17 Ngeneric:Invisible-Pin|pin@1||-1.5|19.5|||||ART_message(D5G4;)Stwin two input latch with one amplifier
  18 Ngeneric:Invisible-Pin|pin@2||0.5|24.5|||||ART_message(D5G6;)Sdata2inTwin10A
  19 NWire_Pin|pin@26||-2|6||||
  20 NWire_Pin|pin@27||-2|-6||||
  21 NBus_Pin|pin@28||-6.5|-2|-1|-1||
  22 NBus_Pin|pin@29||-6.5|-1|-1|-1||
  23 NBus_Pin|pin@30||-6.5|2|-1|-1||
  24 NBus_Pin|pin@31||-6.5|1|-1|-1||
  25 Awire|net@91|||900|pin@26||-2|6|lat[1:2]|hcl[B]|-2|3
  26 Awire|net@92|||1800|conn@1|y|-7.5|-6|pin@27||-2|-6
  27 Awire|net@93|||2700|pin@27||-2|-6|lat[1:2]|hcl[A]|-2|-3
  28 Abus|net@94||-0.5|IJ1800|conn@0|y|-9.5|-2|pin@28||-6.5|-2
  29 Abus|net@95||-0.5|IJ2700|pin@28||-6.5|-2|pin@29||-6.5|-1
  30 Abus|net@96||-0.5|IJ1800|pin@29||-6.5|-1|lat[1:2]|inA[1]|-3|-1
  31 Abus|net@97||-0.5|IJ1800|conn@5|y|-10|2|pin@30||-6.5|2
  32 Abus|net@98||-0.5|IJ900|pin@30||-6.5|2|pin@31||-6.5|1
  33 Abus|net@99||-0.5|IJ1800|pin@31||-6.5|1|lat[1:2]|inB[1]|-3|1
  34 Awire|net@102|||1800|conn@6|y|-7|6|pin@26||-2|6
  35 Abus|net@103||-0.5|IJ0|conn@4|a|9.5|0|lat[1:2]|out[1]|3|0
  36 Ehcl[A]||D4G2;|conn@1|a|I
  37 Ehcl[B]||D4G2;|conn@6|a|I
  38 EinA[1:2]||D4G2;|conn@0|a|I
  39 EinB[1:2]||D4G2;|conn@5|a|I
  40 Eout[1:2]||D6G2;|conn@4|y|O
  41 X