chips/marina/electric/latchPartsK.delib/latchAmp09.6B.sch

   1 HlatchPartsK|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LredFive|redFive
   8
   9 # Cell latchAmp09.6B;1{sch}
  10 ClatchAmp09.6B;1{sch}||schematic|1188672817555|1207537027348|
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||-18|0||||
  13 NOff-Page|conn@1||18|0||||
  14 IredFive:inv;1{ic}|inv@0||9|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S9.6|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  15 IredFive:inv;1{ic}|invLT@0||-9|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S4|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  16 Ngeneric:Invisible-Pin|pin@0||-1.5|24.5|||||ART_message(D5G6;)SlatchAmp09.6B
  17 Ngeneric:Invisible-Pin|pin@1||-2.5|15.5|||||ART_message(D5G3;)Sies 7 April 2008
  18 Ngeneric:Invisible-Pin|pin@2||-3.5|19.5|||||ART_message(D5G4;)Sfor new latch
  19 IorangeTSMC090nm:wire90;1{ic}|wire90@1||0|0|||D0G4;|ATTR_L(D5G1;PUD)D114.70000000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  20 Awire|net@85|||0|invLT@0|in|-11.5|0|conn@0|y|-16|0
  21 Awire|net@88|||1800|wire90@1|b|2.5|0|inv@0|in|6.5|0
  22 Awire|net@89|||0|wire90@1|a|-2.5|0|invLT@0|out|-6.5|0
  23 Awire|net@96|||1800|inv@0|out|11.5|0|conn@1|a|16|0
  24 Ein||D4G2;|conn@0|a|I
  25 Eout[1]||D6G2;|conn@1|y|O
  26 X